Year: 2025
Type: article
Abstract: This letter presents a unified phase- and voltage-domain modeling framework for type-II double-sampling phase-locked loops (DSPLLs). An improved analytical phase-domain model is derived by refining the phase detector's transfer function. A Verilog-A based voltage-domain model is developed, enabling fast transient-only phase noise analysis. We clarify the noise contribution of the S/H clocks. We further extend the reference phase noise 3dB-reduction theory, revealing its degradation under asymmetric sampling slew rates. The phase- and voltage-domain models validate each other and offer useful guide for DSPLLs design optimization.
Source: IEICE Electronics Express
Authors: Longbiao Wang, Ming Che, Peng Chen, Menglian Zhao, Xiaopeng Yu, Xiongchuan Huang
Institutions: Fudan University, University College Dublin, Zhejiang University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4416831797