Work

A new bit-serial multiplier architecture for area-efficient fpga implementation.

Year: 2004

Type: article

Source: Circuits, Signals, and Systems

Authors: Luc Morin, Rachid Beguenane, Stéphane Simard, Éric Larouche

Language: English

Topic: Cryptography and Residue Arithmetic

Subfield: Information Systems

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W47178991

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Related to: 10