Work

A Comprehensive Survey of Clock-Gating Techniques for Low-Power VLSI Design

Year: 2025

Type: conference-paper

Source: International Conference on Electronics, Communication and Aerospace Technology (ICECA)

DOI: 10.1109/iceca66444.2025.11383489

Authors: D.V.N.Bharathi, Bala Sindhuri Kandula, Vignesh Naga Trinadh Kalepu, Yashwanth Korada, Tejaswi Kammila, Manikanta Santhosh Kanchi

Institution: SRKR Engineering College

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W7128805249

FWCI: 8.86

Cites: 20

Cited by: 5

Related to: 10