Work

Reliability Investigation of High Performance Nanoscale Dual Edge Triggered (DET) TSPC-D-Flip Flops for Future Low Power Electronics

Year: 2025

Type: conference-paper

Source: IEEE International Conference on Green Industrial Electronics and Sustainable Technologies (GIEST)

DOI: 10.1109/giest66547.2025.11387207

Authors: Md. Badhesha, Motla Sathwika, J. Ajayan

Institution: SR University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Affordable and clean energy

Open Access status: closed

OpenAlex ID: W7130712867

FWCI:

Cites: 12

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Related to: 10