Work

A Fully Integrated High-PSRR LDO with Cascaded NMOS-PMOS Buffer Architecture in 180 nm CMOS

Year: 2026

Type: conference-paper

Source: International Conference on VLSI Design

DOI: 10.1109/vlsid68508.2026.00073

Authors: Kaire Anupama, Patri Sreehari Rao

Institution: National Institute of Technology Warangal

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: Ministry of Electronics and Information technology

OpenAlex ID: W7137998640

FWCI: 28.11

Cites: 13

Cited by: 1

Related to: 10