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D3OF: DRL-Driven Dual-Layer Dynamic Obfuscation Framework for FPGAs

Year: 2026
Type: conference-paper
Abstract: The reverse engineering of FPGA bitstream configuration files poses numerous security threats such as intellectual property (IP) piracy and hardware Trojan insertion. However, existing hardware obfuscation techniques against bitstream reverse engineering generally suffer from several drawbacks, including insufficient robustness against Boolean Satisfiability (SAT) attacks, the difficulty in balancing hardware overhead and security performance, and poor cross-architecture compatibility. To tackle these challenges, this paper proposes a DRL-driven dual-layer dynamic obfuscation framework for FPGAs (D3OF). First, a collaborative mechanism integrating a logic obfuscation layer and a dynamic perturbation layer is designed, with four key parameters (LUT row permutation ratio, redundant input expansion bit-width, routing switching frequency, PDU delay step-size) defined to comprehensively disrupt the bitstream-function mapping. Second, a PPO-based optimization model is constructed, transforming multi-dimensional parameter tuning into a Markov Decision Process (MDP) to achieve Pareto optimality between security and overhead. Experiments on the Xilinx Artix-7 FPGAs with the AES-128 circuit show that the proposed PPO algorithm reduces search time by 41.1% and 31.5% compared with GA and PSO, respectively, with a Pareto distance as low as 0.07 and no local optima. Even under full-strength obfuscation, the increases in hardware overhead are controlled within 18% for area, 8% for latency, and 12% for power consumption. Featuring strong architectural adaptability and configurable security levels, this method provides a dynamically efficient, intelligently optimized anti-reverse-engineering solution for FPGAs in critical fields.
Language: English
Open Access status: hybrid
OpenAlex ID: W7166309079
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Cites: 25
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Related to: 10