Federated Learning-Based Smart Routing Framework for Secure VLSI Physical Design
Year: 2026
Type: article
Abstract: This review paper offers a state-of-the-art meta-analysis of the recent utilization of federated learning (FL) throughout secure VLSI physical design and smart routing frameworks. The semiconductor industry is experiencing growing challenges with protecting intellectual property as well as managing distributed design workflows, and federated learning presents a new paradigm to achieve collaborative circuit optimization without needing to centralize sensitive design data. This work summarizes FL-based routing algorithms, security techniques and optimization approaches to enhance performance. We survey 30 peer-reviewed papers across the domains of machine learning, circuit design, network optimization and cybersecurity. This survey shows that federated learning can be integrated with conventional routing methods to improve security and efficiency via privacy-preserving collaborative design optimization. The highlights show that FL-based frameworks designs require 15-30% less time for design than traditional EDA-based and the protection against adversarial attacks and IP loss, respectively. But problems for convergence efficiency, communication overhead and heterogeneous hardware deployment also remain. This paper outlines important open challenges, highlights future directions for secure VLSI design automation, and surveys the potential impact of federated learning on future chip design workflows.
Authors: Raturi, Vikas, Alam, M. Zahid
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7201876339