Neuronflow V2: Sparse and Energy Efficient Event-driven AI Processing
Year: 2026
Type: article
Abstract: Neuronflow V2 is a processor designed for efficient, low-latency AI inference by exploiting activation sparsity. Its event-driven, input-stationary architecture minimizes unnecessary computations, achieving millisecond latency and under 500 mW power for computer-vision models on edge devices. We show how sparsity-inducing training and thresholding enhance activation sparsity, allowing Neuronflow V2 to reduce energy use and latency while maintaining accuracy. We use Neural Architecture Search to re-balance weight and activation memory requirements, enabling effective temporal sparsity exploitation. Fabricated in 5nm at 800 MHz, Neuronflow V2 demonstrates scalable, energy-efficient brain-inspired performance on silicon.
Source: IEEE Micro
Institution: Snap (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $2,995
OpenAlex ID: W7202250324