A Simple Layout Scheme to Enhance the ESD Robustness of UHV-LDMOS Devices in HVICs
Year: 2026
Type: conference-paper
Abstract: Conventional ultra-high-voltage (UHV) LDMOS devices exhibit poor electrostatic-discharge (ESD) stress and therefore cannot adequately protect themselves from ESD damage. This work proposes a simple, layout-only technique that significantly enhances the ESD robustness of UHV-LDMOS devices used in high-voltage integrated circuits (HVICs). The method enables meeting a 2-kV ESD-specification without requiring any process modification or area penalty. The key idea is to divide a long diffusion strap into multi single-contact diffusion segments, each acting as an individual fuse that locally clamps the ESD current during an ESD event. This segmentation improves current uniformity and enhances overall ESD robustness.
Institution: Vanguard International Semiconductor (Taiwan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7204097288