UVM based DPLL using System Verilog
Year: 2026
Type: conference-paper
Abstract: The Digital Phase-Locked Loop (DPLL) finds applications in a variety of digital system implementations due to its flexibility, scalability and compatibility with programmable hardware components. This paper deals with the design, verification and FPGA implementation of a completely digital Phase-Locked Loop (DPLL) utilizing Verilog HDL programming language and Universal Verification Methodology (UVM) based SystemVerilog environment. The architecture includes a Numerically Controlled Oscillator (NCO), phase detector, loop filter, period measurement block and lock detection scheme which provides for continuous adjustment of the output frequency and thus, stable locking to the reference clock. The UVM verification framework is implemented including such components as a sequence generator, driver, monitor, scoreboard and functional coverage to verify the design operation. The functional coverage and code coverage for the design are achieved at 100%, providing complete verification of its functionality. The design is then synthesized and implemented on the Artix-7 FPGA chip. The lock operation is verified by means of the LED indicator, proving reliability of its operation in real time mode.
Institutions: Chaitanya Bharathi Institute of Technology, SR University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7204097457