Hardware-Efficient Scalable Probabilistic Circuits Utilizing Cost Functions on FPGA
Year: 2026
Type: article
Abstract: Probabilistic computing based on invertible logic leverages p-bits to construct circuits capable of bidirectional operation. This work introduces a novel methodology for generating the weight matrix of invertible logic circuits using cost functions. A design framework is proposed, spanning from cost function formulation to simulation and FPGA-based hardware implementation. The constructed weight matrices are scalable to higher-bit circuits using algorithms derived from the derived constraints of the cost-function-based design. Hardware implementations, including synthesis and simulation results are presented to validate the functionality and efficiency of the proposed circuits. Key functions such as ReLU, majority, multiplexer, decoder, averaging function, and bitcount are constructed using a minimal number of p-bits, with no intermediate p-bits, resulting in low graph density. The proposed 10-bit ReLU implementation utilizes twenty p-bits, achieving a 52% reduction in non-zero matrix elements and a 60% decrease in graph density. The weight matrices are optimized to reduce the number of non-zero elements, resulting in reduced resource utilization in terms of LUTs and flip-flops on the FPGA. The system behavior is governed by the inverse temperature parameter$\beta$, which controls the exploration–convergence trade-off. Intermediate values ($0.3 \leq \beta \leq 0.7$) achieve an optimal balance between exploration and convergence.The XOR functionality is implemented using a neural network, where system converges to correct outputs with high accuracy across forward and invertible modes. In particular, the FPGA implementation of ReLU utilizes 1,493 LUTs and 180 flip-flops, resulting in a 35% reduction in LUT usage and a 68% reduction in flip-flops. The proposed cost function-based invertible circuits consume fewer resources and offer scalability to n-bit implementations compared to other methodologies.
Authors: Amit Singh, Amit Kumar Jangid, B. Srinivasu
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $2,645
OpenAlex ID: W7204172950