Work

A Stacked Top Select Gate Architecture for High-Density 3-D nand Flash

Year: 2026

Type: article

Abstract: In the pursuit of higher density 3Dnandflash memory arrays, the “sacrificial holes” necessitated by traditional top select gate (TSG) for solid isolation present an enduring challenge to scaling. To overcome this barrier, this study proposes a novel TSG architecture featuring an independent stack design, which can reduce the channel to dielectric spacing to satisfy isolation requirements while eliminating “sacrificial holes” and significantly increasing storage density. Furthermore, the proposed architecture follows standard design with a solid polysilicon channel structure, relieving complex process demands.

Source: IEEE Electron Device Letters

DOI: 10.1109/led.2026.3728647