Advanced Bus-Clamping SVM Strategy in a 3-phase Quasi-ZSI for Switching Loss Reduction
Year: 2026
Type: conference-paper
Abstract: Conventional space vector pulse-width modulation (CSVPWM) utilizes standard switching sequences in which the zero vector duration is symmetrically distributed between the two zero states within each subcycle. In contrast, existing bus-clamping PWM (BCPWM) strategies employ clamping-based sequences that utilize a single zero state during a subcycle. This study focuses on a distinct category of Advanced bus clamping switching sequences, referred to as the ST4_ABC_MCBC technique, which optimises the switching transition per switching cycle. The proposed PWM technique is implemented in maximum constant boost control (MCBC) approach. Its merits in Quasi-Z Source inverter (Quasi-ZSI) are highlighted and hence reduces the maximum instantaneous inductor current ripple as compared to the ZSVM6_MCBC for the equal average switching frequency. Furthermore, the proposed techniques lead to a reduction in inverter switching losses under high power-factor operating conditions when compared with CSVPWM and conventional BCPWM schemes. To verify the feasibility of the proposed technique in Quasi-ZSI, simulation are carried out and relevant results are presented.
Institution: Termez Institute of Engineering and Technology
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7204862338