FIUSE: NVM-Free Secret Generation for Secure Chip-Scale Embedded Systems using SRAM PUF
Year: 2026
Type: conference-paper
Abstract: Low footprint embedded devices with single-chip microcontrollers, such as embedded RFID tags or single-chip systems, are becoming increasingly relevant for agricultural, implantable biomedical and supply chain tracking applications. The low footprint design requirement dictates which components can be integrated on the system. Relying on off-chip secure elements as a root of trust is, if practical, often not feasible or excessively expensive. Physically Unclonable Functions (PUFs) are commonly used to store or generate unique device secrets leveraging intrinsic nanometer-scale process variations. Existing reliable extraction methods still require Non-Volatile Memory (NVM) to store helper data, necessary to re-generate the secret from a noisy PUF response. These methods require either an off-chip memory or an expensive fabrication process that supports NVM integration. NVM-free PUF-based secret generation enables trusted computing on constrained embedded systems, while reducing fabrication costs. This paper proposes FIUSE, a standalone on-chip security peripheral that can be fabricated in common CMOS processes. This paper shows the feasibility of an NVM-free secret generator based on SRAM PUF, and gives insights on trade-offs between security, performance and resource utilization. This paper contributes with an open-source hardware implementation, from RTL to GDS, ready to be integrated with a RISC-V processor and manufactured in the IHP-SG13G process. FIUSE relies only on standard SRAM macros, which makes it portable to other technologies, and conventional cryptography functions can be easily added while remaining compatible with fabrication in regular CMOS processes.
Source: HAL
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7213700262