Low Leakage CMOS Circuits Using a 22 Nm NMOS Based Clock Gating Technique
Year: 2026
Type: conference-paper
Abstract: Clock gating is an effective technique to reduce dynamic power feasting in CMOS circuits. An NMOS-based clock gating approach studied at a 22 nm technology node to minimize redundant switching activity and leakage current. The proposed circuit includes CMOS NAND, NOR, and full adder circuits structured by an NMOS-gated clock signal. The Simulated results demonstrate substantial leakage reduction, where NAND leakage current drops from 5.2 nA to 1.4 nA, NOR from 4.8 nA to 1.2 nA, and full adder from 6.5 nA to 2.1 nA. Additionally, transmission delay is enhanced, with reductions from 22 ps to 15 ps for NAND, 25 ps to 17 ps for NOR, and 38 ps to 24 ps for the fulladder. The output voltage levels stay stable as$\text{VOH} \approx 0.94 \mathrm{V}$and$\text{VOL} \approx 0.03 \mathrm{V}$, which ensure reliable logic operation. The outcomes confirm that the suggested NMOS-based clock gating technique successfully reduces power consumption while enhancing execution, making it suitable candidate for next-generation low-power CMOS VLSI systems.
Authors: P. Ranjithkumar, Jarvis. B, Prasenjit Deb
Institution: REVA University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7220659355