Implementation of Range-Doppler Frequency Spectrum Map in FPGA for FMCW Radar Applications
Year: 2026
Type: conference-paper
Abstract: Frequency-Modulated Continuous Wave (FMCW) radar systems are common in the current world with applications like autonomous driving and surveillance because they can easily estimate the range and velocity of targets. Nevertheless, the processing of FMCW radar signals in real-time is computationally intensive and involves a two-dimensional Fast Fourier Transform (2D-FFT) and data processing on a large scale. The paper describes how a full Range-Doppler signal processing chain can be implemented on an FPGA platform, with a particular emphasis on the effective implementation of hardware and optimization of performance. The first architecture created and tested in both High-Level Synthesis (HLS) and the traditional Register Transfer Level (RTL) design models is a baseline architecture (A1), which is a five-stage processing pipeline that contains windowing, Range FFT, interleaving, and Doppler FFT. To improve the performance, a proposal of an optimized architecture (A2) using the HLS directives PIPELINE and DATAFLOW is suggested to use parallelism and accelerate the throughput. The system is realized on the Xilinx Zynq based FPGA with the help of the AXI interfaces to provide effective data transfer. The experimental findings indicate that the optimized architecture has better timing performance and accuracy in Range-Doppler estimation. The suggested design reveals the efficiency of FPGA acceleration through HLS-based designs to obtain real-time radar signal processing.
Institutions: Amrita Vishwa Vidyapeetham, Bennett University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7220734844