A 1.22 fJ/bit/Search Shared BL/SL Single-Ended 32×32 CAM Using 40-nm CMOS Process
Year: 2026
Type: article
Abstract: This paper presents a fully integrated, energy-efficient$32\times 32$content addressable memory (CAM) based on single-ended memory cells to realize an access and search architecture with a shared bit-line and search-line (BL/SL). Traditional CAMs depend on differential bit-lines and search-lines, which introduce excessive routing capacitance, power consumption, and redundant switching activity. To address these issues, the proposed design combines read, write and search signaling into a single physical line and adopts single-ended operation throughout the write, read, and search modes. A dynamic voltage scaling (DVS) controller manages local supply voltage at the column level for each CAM cell to reduce standby leakage power, while a regenerative sense amplifier (Re-SA) aids full-swing match line sensing under low-voltage operation. Furthermore, an on-chip built-in self-test (BIST) architecture is also integrated to improve observability, controllability, and silicon validation efficiency. The proposed CAM is implemented using TSMC 40-nm CMOS technology and confirmed through post-layout simulations and silicon measurements. Measurement results validate the correct read, write, and search functionality of the proposed CAM at a 0.9-V supply voltage, with the fabricated prototype exhibiting a total chip power dissipation of 6.14 mW. It achieves a measured energy efficiency of 1.22 fJ/bit/search with a search time of 2.16ns at a 20-MHz clock frequency. These findings validate the proposed CAM as an energy-efficient solution for lookup-intensive and power-constrained applications.
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $2,645
OpenAlex ID: W7224455010