BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM4 Accelerator
Year: 2026
Type: conference-paper
Abstract: Trusted Platform Modules (TPMs) serve as hardware roots of trust in secure System on Chip (SoC) environments, supporting essential security services such as message confidentiality, digital signatures, authentication, and cryptographic key management. Symmetric block cipher algorithms such as SM4 are fundamental to these operations, yet standalone preintegration validation of AXI based cryptographic accelerators through a serial interface remains unaddressed in existing literature. This research paper presents a reusable SPI-to-AXI standalone validation framework for independent pre-integration verification of AXI enabled cryptographic accelerators. The proposed framework employs dual clock domain synchronization and FIFO based buffering to ensure reliable data transfer between the SPI interface and the AXI enabled SM4 accelerator. The design supports SM4 encryption and decryption across ECB, CBC, CFB, OFB, and CTR modes per GB/T 32907-2016, implemented in Verilog HDL and validated on the Xilinx Virtex UltraScale+ VCU118 FPGA, achieving a 300.00 MHz frequency with 3678 LUTs for the SM4 AXI-IP across all modes, with a throughput of 1.2 Gbps, and ASIC synthesis on SCL 180 nm with 20,790 standard cells and a cell area of 0.622 mm2, confirming silicon readiness of the design. The design further serves as a hardware validation platform within the RISC-V based BHARAT-TPM for validating AXI based cryptographic accelerator cores.
Institution: Centre for Development of Advanced Computing
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W7224869080