BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled SM2-DSA Accelerator
Year: 2026
Type: conference-paper
Abstract: Trusted Platform Modules (TPMs) serve as hardware roots of trust in secure System on Chip (SoC) environments, supporting essential security services such as secure key exchange, digital signatures, authentication, and cryptographic key management. Public key cryptographic algorithms such as the SM2 Digital Signature Algorithm (SM2 DSA) are fundamental to these operations, requiring efficient hardware implementations and communication interfaces. However, standalone preintegration validation of AXI based cryptographic accelerators through a serial interface remains unaddressed in existing literature. This research paper presents a deterministic, reusable hardware validation framework for AXI based cryptographic IP cores, realized as a structured, packet based SPI to AXI validation architecture. The proposed framework employs dual clock domain synchronization and FIFO based buffering to ensure reliable data transfer between the SPI interface and the AXI enabled SM2 DSA accelerator. The architecture supports key generation, signature generation, and signature verification operations using efficient scalar multiplication and modular arithmetic techniques. The design is implemented in Verilog HDL and verified using standard cryptographic test vectors from the GM/T 0003 specification, validated on the Xilinx Virtex UltraScale VCU118 FPGA achieving 125 MHz with 48880 LUTs with ASIC synthesis on SCL 180 nm resulting in 2,62,253 standard cells. The design further serves as a hardware verification platform within the RISC-V based BHARAT-TPM for validating AXI based cryptographic accelerator cores.
Institution: Centre for Development of Advanced Computing
Language: English
Subfield: Information Systems
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W7224947211