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Priyanka Choudhury

Observed name: P. Choudhury
ORCID: 0000-0002-0917-0925
Observed ORCID: 0000-0002-0917-0925
OpenAlex ID: A5002234378
Design and Verification of AMBA AHB
2019 · Perumalla Giridhar, Priyanka Choudhury · International Conference on Advanced Technologies in Intelligent Control, Environment, Computing & Communication Engineering (ICATIECE) · 23
An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together
2012 · Priyanka Choudhury, Sambhu Nath Pradhan · Journal of Low Power Electronics · 12
Low power and high testable Finite State Machine synthesis
2015 · Sambhu Nath Pradhan, Priyanka Choudhury · 9
Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm
2012 · Priyanka Choudhury, Sambhu Nath Pradhan · Lecture notes in computer science · 6
Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power
2016 · Debanjali Nath, Priyanka Choudhury, et al. · Journal of Circuits Systems and Computers · 3
Thermal-Aware Partitioning and Encoding of Power-Gated FSM
2018 · Priyanka Choudhury, Kanchan Manna, et al. · Journal of Circuits Systems and Computers · 2
Thermal aware AND-OR-XOR network synthesis
2015 · Priyanka Choudhury, Debanjali Nath, et al. · International Symposium on VLSI Design and Test (VDAT) · 2
CG-in-PG architecture implementation for power reduction in FSMs
2014 · Priyanka Choudhury, Abhishek Nag, et al. · International Journal of Electronics Letters · 2
Power-area trade-off in power gated FSM synthesis
2016 · Priyanka Choudhury, Sambhu Nath Pradhan · International Journal of Circuits and Architecture Design · 1
Design of new high-speed and low-energy dynamic PLA
2014 · Sambhu Nath Pradhan, Suman Bhowmik, et al. · International Journal of Electronics Letters · 1
Power gating architecture implementation inside clock period to reduce power
2014 · Debanjali Nath, Priyanka Choudhury, et al. · International Journal of Computer Aided Engineering and Technology · 1
Within-clock power gating architecture implimentation to reduce leakage
2012 · Sambhu Nath Pradhan, Debanjali Nath, et al. · International Conference on Computers and Devices for Communication · 1
IoT Integrated Environment Monitoring System with Data Accuracy and Android Application Platform
2026 · Koel Datta Purkayastha, Priyanka Choudhury, et al. · Springer eBooks
GLAD Assisted In2O3 NW-TiO2 NW Heterostructure for Enhanced UV-Vis Absorption
2020 · Vinod Kumar Yadav, Vinit Kumar Yadav, et al. · Lecture notes in electrical engineering
Transistor level realisation of power gated FSM
2017 · Debanjali Nath, Priyanka Choudhury, et al. · International Journal of Computer Aided Engineering and Technology
Transistor level realisation of power gated FSM
2017 · Sambhu Nath Pradhan, Priyanka Choudhury, et al. · International Journal of Computer Aided Engineering and Technology
Power Aware Testing by Proper Don't Care Filling of Test Patterns
2013 · Oindrila Chakraborty, Parna Chakraborty, et al.
Switching Reduction in Power Gated Design
2013 · Priyanka Choudhury, Sambhu Nath Pradhan
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)
2013 · Debanjali Nath, Priyanka Choudhury, et al. · Communications in computer and information science
Thermal aware power gated design
2013 · P. Choudhury, S.N. Pradhan · International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom)
Works count: 20
Citation count: 63
H-index: 4
I10-index: 2
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