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Saroja V. Siddamal

Observed names: Saroja Siddamal, Saroja V Siddamal, Saroja V Siddamal, Saroja V. Siddamal, Saroja. V. Siddamal
Observed institution: KLE Technological University
ORCID: 0000-0002-9579-9980
Observed ORCID: 0000-0002-9579-9980
OpenAlex ID: A5007372645
High speed signed multiplier for Digital Signal Processing applications
2012 · Sandesh S. Saokar, R. M. Banakar, et al. · International Conference on Signal Processing, Computing and Control (ISPCC) · 37
Activity Based Teaching Learning: An Experience
2016 · Ujwala Patil, Saroja V. Siddamal · Journal of Engineering Education/Journal of engineering education transformations/Journal of engineering education transformation · 20
Design and Testing of Combinational Logic Circuits Using Built in Self Test Scheme for FPGAs
2015 · Nagaraj S. Vannal, Saroja V. Siddamal, et al. · International Conference on Communication Systems and Network Technologies · 18
Design of High-Speed Floating Point Multiplier
2008 · Saroja V. Siddamal, R. M. Banakar, et al. · IEEE International Workshop on Electronic Design, Test and Applications (DELTA) · 15
Design of High Speed, Reconfigurable Multiple ICs Tester using FPGA Platform
2018 · Basavaraj Rabakavi, Saroja Siddamal · International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques (ICEECCOT) · 9
Reflective Teaching for Undergraduate Courses: An Experience
2017 · Saroja V. Siddamal, Suneeta V. Budihal, et al. · Journal of Engineering Education/Journal of engineering education transformations/Journal of engineering education transformation · 8
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Framework for intercell interference avoidance in MIMO OFDMA system
2016 · Suneeta V. Budihal, Sandhya R., et al. · International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) · 8
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator
2020 · Mandakini Kadam, Saroja V. Siddamal, et al. · International Symposium on VLSI Design and Test (VDAT) · 7
Towards Sustainable Integrated Model for Skill Development: A Collaborative Approach
2020 · Saroja V Siddamal, Suhas B Shirol, et al. · Procedia Computer Science · 7
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An optimized RISC-V processor with five stage pipelining using Tournament Branch Predictor for efficient performance
2022 · Ananya Choudhury, Saroja V Siddamal, et al. · IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) · 6
Implementation of 32-bit ISA Five-Stage Pipeline RISC-V Processor Core
2022 · Manjunath Kalmath, Akshay Kulkarni, et al. · Algorithms for intelligent systems · 6
A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation
2022 · Jayashree Mallidu, Saroja V. Siddamal · Lecture notes in networks and systems · 5
A Novel March XR Algorithm, Design, and Test Architecture for Memories
2022 · I. G. Matri, Aishwaraya, et al. · Lecture notes in electrical engineering · 5
Enhanced Learning Through Self-Study Component in Engineering Education
2014 · Saroja V. Siddamal, Suneeta V. Budihal, et al. · Springer eBooks · 5
Split Step Method in the Analysis and Modeling of Optical Fiber Communication System
2011 · Saroja V. Siddamal, R. M. Banakar, et al. · Communications in computer and information science · 5
GUI Implementation of Logic Built in Self-Test[LBIST]
2024 · Rohit Kademani, Suhas Shirol, et al. · International Conference for Innovation in Technology (INOCON) · 4
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer
2021 · Dharmaray Nedalgi, Saroja V. Siddamal · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 4
Design and Implementation of Novel Scan Architecture for Test Power Reduction
2020 · Harshavardhan Nekar, Saroja V. Siddamal · Procedia Computer Science · 4
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FPGA Implementation of Systolic Array Architecture for Matrix Multiplication
2024 · Rajeshwari Mattimani, Saroja V. Siddamal, et al. · Lecture notes in networks and systems · 3
Project-Based Learning to Enhance Employability and Entrepreneurship: A Collaborative Approach
2021 · Saroja V Siddamal, Aditya M Despande · World Engineering Education Forum - Global Engineering Deans Council (WEEF-GEDC) · 3
Framework for a Green Campus-LoRa™-Based Low-Power Smart Water Management for Campus
2021 · Saroja V. Siddamal, Vinod Talikoti, et al. · Lecture notes in networks and systems · 3
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology
2019 · Saroja V. Siddamal, Suhas B. Shirol, et al. · Communications in computer and information science · 3
A Survey and Theoretical View on Compressive Sensing and Reconstruction
2016 · SKSVMACET/ECE, Laxmeshwar, 582116, India, Santosh S. Bujari, et al. · International Journal of Image Graphics and Signal Processing · 3
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Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology
2014 · Narayan V. Sugur, Saroja V. Siddamal, et al. · International Conference on VLSI Design · 3
Analysis of Clock Gating Techniques for Low Power
2024 · Abhishek Bhajantri, Suneeta Budihal, et al. · Lecture notes in electrical engineering · 2
Works count: 76
Citation count: 208
H-index: 7
I10-index: 4
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