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S. Saravanan

Observed name: S Saravanan
Institution: SASTRA University
ORCID: 0000-0001-6528-2481
Observed ORCID: 0000-0001-6528-2481
OpenAlex ID: A5011924450
Hybrid Deep Learning Algorithms for Dog Breed Identification—A Comparative Analysis
2023 · B. Valarmathi, N. Srinivasa Gupta, et al. · IEEE Access · 25
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RETRACTED ARTICLE: Analysis of basic neural network types for automated skin cancer classification using Firefly optimization method
2020 · M. Sundar Prakash Balaji, S. Saravanan, et al. · Journal of Ambient Intelligence and Humanized Computing · 24
Chaotic Sea Horse Optimization with Deep Learning Model for lung disease pneumonia detection and classification on chest X-ray images
2024 · V. Parthasarathy, S. Saravanan · Multimedia Tools and Applications · 20
Achieveing reduced area by Multi-bit Flip flop design
2013 · G. Prakash, K. Sathishkumar, et al. · International Conference on Computer Communication and Informatics (ICCCI) · 16
Design and analysis of high speed shift register using Single clock pulse method
2013 · A. Rajaram, P. Premalatha, et al. · International Conference on Computer Communication and Informatics (ICCCI) · 15
Design of Low-Area and High Speed Pipelined Single Precision Floating Point Multiplier
2020 · Thiruvenkadam Krishnan, S. Saravanan · International Conference on Advanced Computing and Communication Systems (ICACCS) · 13
Design and implementation of area efficient EAIC modulo adder
2020 · Thiruvenkadam Krishnan, S. Saravanan, et al. · Materials Today Proceedings · 11
Design and Analysis of Linear Feedback Shift Register Based on Various Tap Connections
2012 · S. Saravanan, M.Lavanya, et al. · Procedia Engineering · 11
Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design
2015 · Sowmithra Vennelakanti, S. Saravanan · Indian Journal of Science and Technology · 9
Recent trends on Post-Silicon validation and debug: An overview
2017 · R Agalya, S Saravanan · International Conference on Networks & Advances in Computational Technologies (NetACT) · 7
Design and analysis of scan power reduction based on linear feedback shift register reseeding
2013 · G. Sowmiya, P. Premalatha, et al. · IEEE Conference on Information and Communication Technologies (ICT) · 6
Implementation of a Novel Data Scrambling based Security Measure in Memories for VLSI Circuits
2015 · R. Vijay Sai, S. Saravanan, et al. · Indian Journal of Science and Technology · 5
Low Power Estimation on Test Compression Technique for SoC based Design
2015 · P. Raja Gopal, S. Saravanan · Indian Journal of Science and Technology · 5
Secured elliptic curve cryptosystems for scan based VLSI architecture
2014 · K. P. Sridhar, M. Raguram, et al. · International Conference on Information Communication and Embedded Systems · 5
Exploring Social Networking Data Sets
2022 · N. Arulkumar, Joy Paulose, et al. · Wiley eBooks · 3
Rectifying Various Scan-based Attacks on Secure IC'S
2015 · C. Ramya, S. Saravanan · Indian Journal of Science and Technology · 3
Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern
2012 · S. Saravanan, Har Narayan Upadhyay · 3
Secure IoT Protocol for Implementing Classified Electroencephalogram (EEG) Signals in the Field of Smart Healthcare
2022 · S. Saravanan, M. Lavanya, et al. · Chapman & Hall/CRC eBooks · 2
A Review on Security in Cache Memories
2016 · R. Vijay Sai, S. Saravanan · Indian Journal of Science and Technology · 2
Low Power Testing based on MOS Design Modified Flip-Flop
2016 · Anjali Chava, S. Saravanan · Indian Journal of Science and Technology · 2
Cell Stability and Power Reduction using Dynamic Isolated Read Static Random Access Memory
2016 · M. S. Vandhana, R. Vijay Sai, et al. · Indian Journal of Science and Technology · 2
Improving the Reliability of Cache Memories using Identical Tag Bits
2016 · S. Manju Bharathi, R. Vijay Sai, et al. · Indian Journal of Science and Technology · 2
Efficient Test Sequence Generator for Area Optimization in LFSR Reseeding
2016 · D. S. Nivetha Joice, S. Saravanan · Indian Journal of Science and Technology · 2
Multiple Scan Base Partitioning Technique to Increase the Throughput in VLSI Testing
2016 · P. Ramalakshmi, S. Saravanan · Indian Journal of Science and Technology · 2
Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design
2012 · S. Saravanan, Har Narayan Upadhyay · Journal of Artificial Intelligence · 2
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Works count: 47
Citation count: 212
H-index: 9
I10-index: 8
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