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Daniil A. Zheleznikov

Observed names: D. A. Zheleznikov, D.A. Zheleznikov, Daniil Aleksandrovich Zheleznikov, Daniil Zheleznikov, Zheleznikov Daniil, Д. А. Железников, Д.А. Железников, Даниил Александрович Железников
ORCID: 0000-0003-2477-1793
Observed ORCID: 0000-0003-2477-1793
OpenAlex ID: A5013950156
Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip
2019 · S. V. Gavrilov, D. A. Zheleznikov, et al. · Russian Microelectronics · 23
Simulated Annealing Based Placement Optimization for Reconfigurable Systems-on-Chip
2019 · Gavrilov Sergey, Zheleznikov Daniil, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 14
Improving Pathfinder Algorithm Perfomance for FPGA Routing
2021 · Mariya A. Zapletina, Daniil A. Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 12
The Hierarchical Approach to Island Style Reconfigurable System-on-a-chip Routing
2020 · IPPM RAS, M.A. Zapletina, et al. · Problems of advanced micro- and nanoelectronic systems development · 12
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Clustering optimization based on simulated annealing algorithm for reconfigurable systems-on-chip
2018 · Sergey Gavrilov, Daniil Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 12
The Acceleration Techniques for the Modified Pathfinder Routing Algorithm on an Island-Style FPGA
2022 · Mariya A. Zapletina, Daniil A. Zheleznikov · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 9
Solving the Problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip
2018 · S. V. Gavrilov, D. A. Zheleznikov, et al. · Russian Microelectronics · 7
Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip
2018 · IPPM RAS, S.V. Gavrilov, et al. · Problems of advanced micro- and nanoelectronic systems development · 7
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The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs
2018 · IPPM RAS, D.A. Zheleznikov, et al. · Problems of advanced micro- and nanoelectronic systems development · 7
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Solution of Interconnect Trace Tasks with Resynthesis for Reconfig-urable Systems-on-Chip
2017 · S.V. Gavrilov, D.A. Zheleznikov, et al. · Proceedings of Universities ELECTRONICS · 7
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Development of an IP-cores Libraries as Part of the Design Flow of Integrated Circuits on FPGA
2021 · Vasilii M. Khvatov, Daniil A. Zheleznikov · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 6
Application of SAT Approach to Switch Blocks Routing for Reconfigurable System-on-a-chip
2020 · IPPM RAS, D.V. Zhukov, et al. · Problems of advanced micro- and nanoelectronic systems development · 5
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Маршрут топологического синтеза для реконфигурируемых систем на кристалле специального назначения
2019 · С. В. Гаврилов, Д. А. Железников, et al. · Микроэлектроника · 5
Digital Circuits Resynthesis Approach for FPGAs Based on Logic Cell with Built-In Flip-Flop
2019 · I.V. Tiunov, I.A. Lipatov, et al. · Problems of advanced micro- and nanoelectronic systems development · 5
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Development and Comparative Analysis of Placement Methods for Reconfigurable Systems-on-a-Chip
2020 · S.V . Gavrilov, D.A. Zheleznikov, et al. · Proceedings of Universities ELECTRONICS · 4
Development and Verification of Various Formats of Functional Blocks Libraries as a Part of the Design Flow for FPGAs
2019 · Tatiana V. Garbulina, Vasiliy M. Khvatov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 4
Development of the Trusted Tools for IC Design on Heterogeneous FPGAs
2023 · Sergey Vitalievich Gavrilov, Daniil Aleksandrovich Zheleznikov, et al. · Proceedings of the Institute for System Programming of RAS · 3
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The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip
2020 · Mariya A. Zapletina, Daniil A. Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 3
The Iterative SAT Based Approach to Detailed Routing for Reconfigurable System-on-a-Chip
2020 · Denis V. Zhukov, Daniil A. Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 3
Analysis of the Programmable Soft IP-cores Implementation for FPGAs
2021 · Vasilii M. Khvatov, Daniil A. Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 2
FPGA Routing Architecture Estimation Models and Methods
2020 · R.Zh. Chochaev, D.A. Zheleznikov, et al. · Proceedings of Universities ELECTRONICS · 2
Post-Route Performance Estimation Method for Reconfigurable Systems-on-a-Chip
2020 · Sergey V. Gavrilov, Vasilii M. Khvatov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 2
Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip
2020 · IPPM RAS, S.V. Gavrilov, et al. · Problems of advanced micro- and nanoelectronic systems development · 2
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Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs
2018 · IPPM RAS, I.V. Tiunov, et al. · Problems of advanced micro- and nanoelectronic systems development · 2
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Simulated Annealing Based Placement in FPGAs with a Modified Permutation Operator and Congestion Optimization
2024 · Rustam Zh. Chochaev, Vladislav A. Zhuravlev, et al. · IEEE International Conference on Problems of Informatics, Electronics and Radio Engineering (PIERE) · 1
Works count: 33
Citation count: 161
H-index: 7
I10-index: 5
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