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Fumihiko Tachibana

Observed names: F Tachibana, F. Tachibana, Fumihiko TACHIBANA, Tachibana, Fumihiko
ORCID: 0000-0002-6311-9215
Observed ORCID: 0000-0002-6311-9215
OpenAlex ID: A5021907697
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology
2008 · Shuou Nomura, Fumihiko Tachibana, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 54
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
2011 · Yusuke Niki, Atsushi Kawasumi, et al. · IEEE Journal of Solid-State Circuits · 40
Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin
2005 · Fumihiko Tachibana, Toshiro Hiramoto · Japanese Journal of Applied Physics · 40
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A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
2013 · Fumihiko Tachibana, Osamu Hirabayashi, et al. · IEEE Journal of Solid-State Circuits · 20
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC
2013 · Jun Deguchi, F. Tachibana, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 17
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision
2018 · Asuka Maki, Daisuke Miyashita, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 16
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design
2008 · Fumihiko Tachibana, Hironori Sato, et al. · Custom Integrated Circuits Conference · 14
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR
2022 · Fumihiko Tachibana, Huy Cu Ngo, et al. · European Solid-State Circuits Conference (ESSCIRC) · 11
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs
2012 · Atsushi Kawasumi, Yasuhisa Takeyama, et al. · Symposium on VLSI Circuits · 10
Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin
2004 · Fumihiko Tachibana, Toshiro Hiramoto · International Conference on Solid State Devices and Materials (SSDM) · 10
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit
2013 · F. Tachibana, O. Hirabayashi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems
2019 · Yuta Tsubouchi, Daisuke Miyashita, et al. · IEEE Journal of Solid-State Circuits · 7
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction
2012 · A. Kawasumi, Y. Takeyama, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 6
Weight Compression MAC Accelerator for Effective Inference of Deep Learning
2020 · Asuka MAKI, Daisuke MIYASHITA, et al. · IEICE Transactions on Electronics · 5
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A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access
2011 · K. Kushida, O. Hirabayashi, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 5
Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN
2021 · Kengo Nakata, Daisuke Miyashita, et al. · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · 3
Can in-memory/analog accelerators be a silver bullet for energy-efficient inference?
2019 · J. Deguchi, D. Miyashita, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems
2018 · Yuta Tsubouchi, Daisuke Miyashita, et al. · Symposium on VLSI Circuits · 3
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision
2019 · Kengo Nakata, Asuka Maki, et al. · IEEE International Symposium on Circuits and Systems proceedings · 2
A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers
2010 · Y Niki, A Kawasumi, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 2
Prune or quantize? Strategy for Pareto-optimally low-cost and accurate CNN
2019 · Kengo Nakata, Daisuke Miyashita, et al. · 1
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit
2013 · Keiichi Kushida, Fumihiko Tachibana, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 1
Circuit techniques to improve disturb and write margin degraded by MOSFET variability in high-density SRAM cells
2011 · Tomoaki Yabe, Atsushi Kawasumi, et al. · Symposium on VLSI Technology · 1
A low-power multi-core media co-processor for mobile application processors
2009 · Shuou Nomura, Fumihiko Tachibana, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 1
Fine-Tuning a KV Cache Concatenation-Aware Model or Recomputing KV Caches? Why Not Both?
2026 · Tachibana, Fumihiko, Miyashita, Daisuke, et al. · arXiv (Cornell University)
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Works count: 30
Citation count: 280
H-index: 10
I10-index: 10
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