Product
Help
Pricing
About
Jobs
Log in
Get started
Author
Add to collection
Gweltaz Gaudin
Observed names:
G GAUDIN,
G. Gaudin,
Gaudin, Gweltaz
Institution:
Soitec (France)
Observed institutions:
Soitec (France),
Université de Tours,
Commissariat à l'Énergie Atomique et aux Énergies Alternatives,
IMEC,
Laboratoire d'Électronique des Technologies de l'Information,
Université Grenoble Alpes
show all 6
ORCID:
0000-0003-4394-4610
Observed ORCID:
0000-0003-4394-4610
OpenAlex ID:
A5023518662
An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization
2011
·
L. Di Cioccio
, P. Gueguen
, et al.
·
Journal of The Electrochemical Society
·
96
PDF
Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking
2010
·
I. Radu
, D. Landru
, et al.
·
IEEE International D Systems Integration Conference
·
36
150 mm SiC Engineered Substrates for High-Voltage Power Devices
2022
·
Séverin Rouchier
, Gweltaz Gaudin
, et al.
·
Materials science forum
·
29
PDF
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
2018
·
A. Vandooren
, J. Franco
, et al.
·
Symposium on VLSI Technology
·
28
300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology
2016
·
Julie Widiez
, Sébastien Sollier
, et al.
·
Japanese Journal of Applied Physics
·
26
PDF
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
2022
·
A. Vandooren
, N. Parihar
, et al.
·
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
·
23
3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
2020
·
A. Vandooren
, Z. Wu
, et al.
·
Symposium on VLSI Technology
·
21
3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
2018
·
A. Vandooren
, J. Franco
, et al.
·
IEEE Transactions on Electron Devices
·
17
Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment
2010
·
Gweltaz Gaudin
, Gregory Riou
, et al.
·
IEEE International D Systems Integration Conference
·
17
(Invited) An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization
2010
·
Lea Di Cioccio
, P. Gueguen
, et al.
·
ECS Transactions
·
16
A simple model for boron trapping by He implantation extended defects in Si: the role of boron diffusivity
2003
·
F CAYREL
, D ALQUIER
, et al.
·
Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms
·
14
Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
2019
·
A. Vandooren
, Z. Wu
, et al.
·
Symposium on VLSI Technology
·
10
Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
2023
·
I. Radu
, B-Y. Nguyen
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
9
Novel low temperature 3D wafer stacking technology for high density device integration
2013
·
I. Radu
, G. Gaudin
, et al.
·
European Solid-State Device Research Conference
·
9
Study towards integration of In0.53Ga0.47As on 300 mm Si for CMOS sub-7 nm node: Development of thin graded In Ga1−As buffers on GaAs
2016
·
Y. Mols
, B. Kunert
, et al.
·
Journal of Crystal Growth
·
8
Wafer Level 3D Stacking Using Smart Cut and Metal-Metal Direct Bonding Technology
2013
·
Lea Di Cioccio
, Ionut Radu
, et al.
·
ECS Transactions
·
8
PDF
SmartSiC™ for Manufacturing of SiC Power Devices
2022
·
N. Daval
, A. Drouin
, et al.
·
IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
·
7
3D sequential integration: applications and associated key enabling modules (design & technology)
2021
·
P. Batude
, O. Billoint
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
7
3D monolithic integration: Stacking technology and applications
2015
·
Ionut Radu
, Bich-Yen Nguyen
, et al.
·
IEEE International Conference on IC Design and Technology (ICICDT)
·
7
(Invited) Low Temperature Direct Bonding 3D Stacking Technologies for High Density Device Integration
2013
·
Lea Di Cioccio
, Ionut Radu
, et al.
·
ECS Transactions
·
5
PDF
AFM study of the SIMS beam induced roughness in monocrystalline silicon in presence of initial surface or bulk defects of nanometric size
2006
·
B. Fares
, C. Dubois
, et al.
·
Applied Surface Science
·
5
A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development
2021
·
M. Alepidis
, I. Ionica
, et al.
·
Solid-State Electronics
·
4
PDF
300 mm InGaAsOI substrate fabrication using the Smart CutTM technology
2015
·
S. Sollier
, J. Widiez
, et al.
·
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
·
4
Boron interaction with extended defects induced by He–H co-implantation in Si
2005
·
G. Gaudin
, F. Cayrel
, et al.
·
Materials Science and Engineering B
·
4
Pre bonding metrology solutions for 3D integration
2010
·
Gregory Riou
, Gweltaz Gaudin
, et al.
·
IEEE International D Systems Integration Conference
·
3
Show more works
View as search
Works count:
40
Citation count:
428
H-index:
11
I10-index:
12
Year
Topic
Type
