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Author

Rahul Pal

ORCID: 0000-0003-2247-0129
Observed ORCID: 0000-0003-2247-0129
OpenAlex ID: A5026745911
Novel CMOS multi-bit counter for speed-power optimization in multiplier design
2018 · Aloke Saha, Rahul Pal, et al. · AEU - International Journal of Electronics and Communications · 41
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
2006 · B. Greene, Qingqing Liang, et al. · Symposium on VLSI Technology · 39
Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication
2019 · Aloke Saha, Rahul Pal, et al. · Micro and Nanosystems · 6
Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer
2022 · Aloke Saha, Rahul Pal, et al. · Micro and Nanosystems · 5
Novel 9:1 Ternary Multiplexer on 32nm CMOS Technology
2021 · Rahul Pal, Rakesh Kumar Singh, et al. · Devices for Integrated Circuit (DevIC) · 3
Novel, robust and efficient CMOS double-base adder
2025 · Rahul Pal, Jayanta Ghosh, et al. · International Journal of Electronics Letters · 1
Novel Low-PDP CMOS Double-Base Comparator
2024 · Rahul Pal, Jayanta Ghosh, et al. · IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE) · 1
Power Efficient Novel CMOS Double-base to Binary Encoder (DBE)
2024 · Rahul Pal, Jayanta Ghosh, et al. · International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S) · 1
Novel Self-Pipelining Strategy for Efficient Multiplication
2019 · Rahul Pal, Jayanta Ghosh, et al. · Devices for Integrated Circuit (DevIC) · 1
New efficient CMOS binary-to-optimum Double-Base Encoder
2026 · Rahul Pal, Jayanta Ghosh, et al. · International Journal of Electronics Letters
Novel low PDP CMOS Double-Base Multiplier
2024 · Rahul Pal · Journal of Electrical Systems
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Works count: 11
Citation count: 98
H-index: 4
I10-index: 2
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