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Marcel Broekaart
Observed names:
Broekaart, M.,
M Broekaart,
M. Broekaart,
M. E. I. Broekaart,
M.E.I. Broekaart
Institution:
Soitec (France)
Observed institutions:
Soitec (France),
STMicroelectronics (France),
Philips (Netherlands),
Signify (Netherlands),
Philips (France),
Delft University of Technology
show all 6
OpenAlex ID:
A5031148101
Coherent electron focusing with quantum point contacts in a two-dimensional electron gas
1989
·
H. van Houten
, C. W. J. Beenakker
, et al.
·
Physical review. B, Condensed matter
·
345
PDF
Observation of zero-dimensional states in a one-dimensional electron interferometer
1989
·
B. J. van Wees
, L. P. Kouwenhoven
, et al.
·
Physical Review Letters
·
339
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm 2 6T-SRAM bitcell
2007
·
C. Fenouillet-Beranger
, J. Todeschini
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
73
Magnetoresistance in a GaAs- Alx Ga1−x As heterostructure with double subband occupancy
1988
·
H. van Houten
, J. G. Williamson
, et al.
·
Physical review. B, Condensed matter
·
70
Hot-electron spectrometry with quantum point contacts
1990
·
J. G. Williamson
, H. van Houten
, et al.
·
Physical review. B, Condensed matter
·
48
Characterization and integration of a CVD porous SiOCH (k<2.5) with enhanced mechanical properties for 65 nm CMOS interconnects and below
2004
·
L.L. Chapelon
, V. Arnal
, et al.
·
Microelectronic Engineering
·
40
Mechanism of Edge Bonding Void Formation in Hydrophilic Direct Wafer Bonding
2013
·
A. Castex
, M. Broekaart
, et al.
·
ECS Solid State Letters
·
34
PDF
A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform
2004
·
F. Arnaud
, F. Boeuf
, et al.
·
Symposium on VLSI Technology
·
31
Low cost 65nm CMOS platform for Low Power & General Purpose applications
2004
·
F. Arnaud
, B. Duriez
, et al.
·
Symposium on VLSI Technology
·
31
Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels
2006
·
C. Gallon
, C. Fenouillet-Beranger
, et al.
·
Japanese Journal of Applied Physics
·
27
PDF
Electron beam direct write lithography flexibility for ASIC manufacturing: an opportunity for cost reduction (Keynote Paper)
2005
·
L. Pain
, M. Jurdit
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
17
0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications
2005
·
F. Boeuf
, F. Arnaud
, et al.
·
Symposium on VLSI Technology
·
16
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2005
·
B. Tavel
, B. Duriez
, et al.
·
European Solid-State Device Research Conference
·
16
Line resistance behaviour in narrow lines patterned by a TiN hard mask spacer for 45 nm node interconnects
2004
·
W.F.A. Besling
, M. Broekaart
, et al.
·
Microelectronic Engineering
·
15
Integration of Low‐ k Dielectric Films in Damascene Processes
2007
·
R.J.O.M. Hoofman
, V.H. Nguyen
, et al.
·
Wiley eBooks
·
13
Injection of ballistic hot electrons and cool holes in a two-dimensional electron gas
1990
·
J.G. Williamson
, H. van Houten
, et al.
·
Surface Science
·
11
PDF
65 nm Device Manufacture Using Shaped E-Beam Lithography
2004
·
Laurent Pain
, Murielle Jurdit
, et al.
·
Japanese Journal of Applied Physics
·
10
Edge Bonding Void Free Low Temperature Oxide-Oxide Direct Bonding Process
2011
·
Arnaud Castex
, Marcel Broekaart
, et al.
·
ECS Transactions
·
6
PDF
Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction
2003
·
Laurent Pain
, Murielle Charpin
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
6
Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effect
2005
·
W.F.A. Besling
, V. ArnaI
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
4
Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions
2004
·
Laurent Pain
, M. Jurdit
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
4
Comparison between organic spin-on BARC and carbon-containing CVD stack for 65-nm gate patterning
2005
·
Jean-Damien Chapon
, Catherine Chaton
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
3
Distortion Free Wafer Bonding Technology for Backside Illumination Image Sensors
2013
·
Marcel Broekaart
, Arnaud Castex
, et al.
·
ECS Transactions
·
2
Effect of Process Induced Strain in 35 nm FDSOI Devices with Ultra-Thin Silicon Channels
2007
·
C. Gallon
, C. Fenouillet-Beranger
, et al.
·
International Conference on Solid State Devices and Materials (SSDM)
·
2
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2006
·
B. Tavel
, B. Duriez
, et al.
·
Solid-State Electronics
·
2
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Works count:
34
Citation count:
1,167
H-index:
14
I10-index:
17
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