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Author

Hsuan-Hsu Chen

Observed institution: National Sun Yat-sen University
OpenAlex ID: A5031439847
Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure
2011 · Yi-Chuen Eng, Jyi-Tsong Lin, et al. · IEEE Transactions on Electron Devices · 9
A new type of CMOS inverter with Lubistor load and TFET driver for sub-20 nm technology generation
2010 · Hsuan-Hsu Chen, Jyi-Tsong Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 6
Numerical study of performance comparison between junction and junctionless thin-film transistors
2010 · Ching-Yao Pai, Jyi-Tsong Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 5
A novel vertical MOSFET with bMPI structure for 1T-DRAM application
2010 · Cheng-Hsin Chen, Jyi- Lin, et al. · International Symposium on Next-Generation Electronics · 5
Unipolar CMOS inverter based on punch-through effect with two embedded oxide structure
2011 · Chia-Hsien Lin, Jyi-Tsong Lin, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · 4
Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate
2009 · Jyi-Tsong Lin, Chih-Hao Kuo, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 3
Advanced block oxide MOSFETs for 25 nm technology node
2009 · Chih-Hung Sun, Jyi-Tsong Lin, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 3
Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length
2010 · Chih-Hung Sun, Jyi-Tsong Lin, et al. · International Symposium on Next-Generation Electronics · 2
A novel planar-type body-connected FinFET device fabricated by self-align isolation-last process
2010 · Po-Hsieh Lin, Jyi-Tsong Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 2
Design theory and fabrication process of 90nm unipolar-CMOS
2010 · Jyi-Tsong Lin, Hsuan-Hsu Chen, et al. · Silicon Nanoelectronics Workshop (SNW) · 2
A novel poly-Si thin-film transistor with multi-trenched body by using Isotropic-etching for Suppressing Off-State Leakage
2009 · Hsien-Nan Chiu, Jyi-Tsong Lin, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 2
A qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs
2011 · Shih-Wei Wang, Jyi-Tsong Lin, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · 1
Characterization for novel non-traditional CMOS inverter composed of a junctionless NMOSFET and a gated N+-N−-P transistor
2010 · Kuan-Yu Lu, Jyi-Tsong Lin, et al. · International Symposium on Next-Generation Electronics · 1
A novel self-align double gate MOSFET with source/drain tie
2009 · Po-Hsieh Lin, Jyi-Tsong Lin, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 1
A unipolar-CMOS with recessed source/drain load
2011 · Jyi-Tsong Lin, Hsuan-Hsu Chen, et al. · IEEE International Conference on ASIC (ASICON)
Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications
2010 · Cheng-Hsin Chen, Jyi-Tsong Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology
Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications
2010 · Hsien-Nan Chiu, Jyi-Tsong Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology
A new type of CMOS inverter with Lubistor load and NMOS driver
2010 · Jyi-Tsong Lin, Hsuan-Hsu Chen, et al. · International Symposium on Next-Generation Electronics
A novel CMOS inverter composed of a junctionless NMOSFET and a gated N−-N-N+ transistor for ULSI applications
2010 · Kuan-Yu Lu, Jyi-Tsong Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology
Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor
2009 · Hsien-Nan Chiu, Jyi-Tsong Lin, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
Self-aligned SOI MOSFETs with Ω-shaped conductive layer and source/drain-tie
2009 · Jyi-Tsong Lin, Tzu-Feng Chang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs
2009 · Yi-Chuen Eng, Jyi-Tsong Lin, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
The impact of junction depth on vertical sidewall MOSFETs with embedded gate
2009 · Chih-Hao Kuo, Jyi-Tsong Lin, et al. · International Workshop on Junction Technology
Future of planar self-aligned block oxide based MOSFET technology
2009 · Jyi-Tsong Lin, Yi-Chuen Eng, et al. · IEEE International Conference on IC Design and Technology (ICICDT)
Self-Aligned SOl MOSFETswith !!-Shaped Conductive Layer and SourcelDrain-Tie
2009 · Jyi-Tsong Lin, Tzu-Feng Chang, et al.
Works count: 25
Citation count: 46
H-index: 4
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