Product
Help
Pricing
About
Jobs
Log in
Get started
Author
Add to collection
Joseph N. Kozhaya
Observed names:
J. Kozhaya,
J.N. Kozhaya,
Joseph Kozhaya
Institution:
IBM (United States)
Observed institutions:
IBM (United States),
University of Illinois Urbana-Champaign,
University of California, Los Angeles,
IBM Research - Thomas J. Watson Research Center,
IBM Research - Austin
OpenAlex ID:
A5038455045
A multigrid-like technique for power grid analysis
2002
·
J.N. Kozhaya
, S.R. Nassif
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
247
Fast power grid simulation
2000
·
Sani R. Nassif
, Joseph N. Kozhaya
·
ACM/IEEE Design Automation Conference (DAC)
·
166
Multigrid-like technique for power grid analysis
2002
·
J.N. Kozhaya
, S.R. Nassif
, et al.
·
International Conference on Computer Aided Design
·
50
Power estimation for large sequential circuits
2001
·
J.N. Kozhaya
, F.N. Najm
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
31
Accurate power estimation for large sequential circuits
1997
·
Joseph Kozhaya
, Farid N. Najm
·
23
An electrically robust method for placing power gating switches in voltage islands
2004
·
J.N. Kozhaya
, L.A. Bakir
·
Custom Integrated Circuits Conference
·
18
Power supply noise aware workload assignment for multi-core systems
2008
·
Aida Todri‐Sanial
, Malgorzata Marek-Sadowska
, et al.
·
16
Power supply noise aware workload assignment for multi-core systems
2008
·
Aida Todri
, Malgorzata Marek-Sadowska
, et al.
·
14
ESD design automation for a 90nm ASIC design system
2004
·
Ciaran J. Brennan
, Joseph Kozhaya
, et al.
·
Electrical Overstress/Electrostatic Discharge Symposium
·
14
I/O buffer placement methodology for ASICs
2002
·
J.N. Kozhaya
, S.R. Nassif
, et al.
·
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
·
13
Subtractive Router for Tree-Driven-Grid Clocks
2012
·
Haifeng Qian
, Phillip J. Restle
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
12
A chip-level electrostatic discharge simulation strategy
2005
·
Haifeng Qian
, J.N. Kozhaya
, et al.
·
12
Effect of noise on timing or data-pattern dependent delay variation when transmission-line effects are taken into account for on-chip wiring
2007
·
A. Deutsch
, H. H. Smith
, et al.
·
IEEE Workshop on Signal Propagation on Interconnects (SPI)
·
8
Multi-grid methods for power grid simulation
2002
·
S.R. Nassif
, J. Kozhaya
·
IEEE International Symposium on Circuits and Systems proceedings
·
7
PACMAN
2014
·
Nancy Y. Zhou
, Phillip Restle
, et al.
·
4
Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus
2011
·
Joseph Kozhaya
, Phillip Restle
, et al.
·
4
Enhancing AI Governance in Financial Industry through IBM watsonx.governance
2024
·
Souva Majumder
, Anushree Bhattacharjee
, et al.
·
3
PDF
ESD design automation & methodology to prevent CDM failures in 130 & 90nm ASIC design systems
2005
·
Ciaran J. Brennan
, Joseph Kozhaya
, et al.
·
Journal of Electrostatics
·
2
Power network analysis for ESD robustness in a 90nm ASIC design system
2004
·
C.J. Brennan
, J.N. Kozhaya
, et al.
·
Custom Integrated Circuits Conference
·
2
Analysis and Design of Power and Ground Networks for VLSI Circuits
2001
·
Joseph Kozhaya
·
Illinois Digital Environment for Access to Learning and Scholarship (University of Illinois at Urbana-Champaign)
Show more works
View as search
Works count:
20
Citation count:
646
H-index:
12
I10-index:
12
Year
Topic
Type
