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Subrahmanyam Boyapati

Observed name: Boyapati Subrahmanyam
ORCID: 0000-0001-9043-6980
Observed ORCID: 0000-0001-9043-6980
OpenAlex ID: A5039401304
Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation
2017 · Subrahmanyam Boyapati, Jean-Michel Redoute, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 16
Modeling and Design of EMI-Immune OpAmps in 0.18- $\mu$ m CMOS Technology
2016 · Subrahmanyam Boyapati, Jean-Michel Redoute, et al. · IEEE Transactions on Electromagnetic Compatibility · 14
A balanced CMOS OpAmp with high EMI immunity
2014 · Boyapati Subrahmanyam, Devarshi Das, et al. · International Symposium on Electromagnetic Compatibility - EMC Europe (EMC Europe) · 14
Compact CMOS Miller OpAmp With High EMI-Immunity
2020 · Jagapathi Gundla, Subrahmanyam Boyapati, et al. · IEEE Transactions on Electromagnetic Compatibility · 13
A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver
2024 · Chakravarti Bheemisetti, Karunanidhan Pandey, et al. · IEEE Journal of Solid-State Circuits · 11
A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology
2024 · Srinivasa Rao Maram, Subrahmanyam Boyapati, et al. · International Symposium on Quality Electronic Design (ISQED) · 10
Analytical and Experimental Validation of Robustness of the Current Mirrors to EMI
2017 · Naga Surya Anjan Kumar Pudi, Subrahmanyam Boyapati, et al. · IEEE Transactions on Electromagnetic Compatibility · 7
A robust CMOS miller OpAmp with high EMI-immunity
2017 · Subrahmanyam Boyapati, Jean-Michel Redoute, et al. · International Symposium on Electromagnetic Compatibility - EMC Europe (EMC Europe) · 7
Modeling and Design of A Compact Low Power Folded Cascode OpAmp With High EMI Immunity
2021 · Raviteja Kammari, Jagapathi Gundla, et al. · IEEE Transactions on Electromagnetic Compatibility · 6
A highly EMI-immune folded cascode OpAmp in 0.18 μm CMOS technology
2016 · Subrahmanyam Boyapati, Jean-Michel Redoute, et al. · International Symposium on Electromagnetic Compatibility - EMC Europe (EMC Europe) · 6
Modeling and design of an EMI-immune source-buffered Miller OpAmp in 0.18 μm CMOS technology
2017 · Subrahmanyam Boyapati, Jean-Michel Redoute, et al. · International Symposium on Electromagnetic Compatibility - EMC Europe (EMC Europe) · 4
Revisiting ZTC and GZTC in CMOS FinFET Using a Five-DC-Parameter MOSFET Model
2025 · Miguel Coelho, Pedro Toledo, et al. · IEEE Access · 3
A Two Stage Miller OpAmp with Low Voltage Cascode Current Source with High EMI Immunity
2023 · Shivdeep, Sahil Sharma, et al. · International Symposium on Electromagnetic Compatibility - EMC Europe (EMC Europe) · 3
Is There a ZTC Biasing Point in the Leading-Edge FET Intrinsic Gain gmrDS?
2025 · Miguel Coelho, Rafael Martins, et al. · International Young Engineers Forum (YEF-ECE) · 2
A Robustness Analysis of Hot Spots Bias Points on the FinFET: A Simulation-Based Approach
2025 · Rafael Martins, Miguel Coelho, et al. · International Young Engineers Forum (YEF-ECE) · 1
Impact of EMI on the Reliability of Crossbar Architecture-Based Inference in CMOS Technology
2025 · Shivdeep, Subrahmanyam Boyapati, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 1
Modeling and Design of Highly EMI Immune CMOS OpAmp Topologies
2024 · Subrahmanyam Boyapati · International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo) · 1
An Energy-Efficient Hybrid Circuit Design Using Double-Tail Strong-Arm Latch for Full Duplex Communication
2026 · Mursina Khatun, Subrahmanyam Boyapati, et al. · IEEE Transactions on Circuits and Systems I Regular Papers
A 0.32-pJ/bit, Energy-Efficient, and Strong-Arm Latch Hybrid Circuit Topology for Off-Chip Full-Duplex Communication
2026 · Mursina Khatun, Subrahmanyam Boyapati, et al. · IEEE Transactions on Circuits and Systems I Regular Papers
Analysis of the ZTC Bias Points in the FinFET Gate Capacitance and Transition Frequency
2025 · Miguel Coelho, Pedro Toledo, et al.
A 0.9 V StrongARM Latch Comparator with 16 ps Delay and 7.5 fJ/op in 16 nm FinFET CMOS Technology
2025 · Rafael Ferreira, Boyapati Subrahmanyam, et al. · IEEE Nordic Circuits and Systems Conference (NorCAS)
$300 \text{mV}-V_{D D}$, nw-Power, ST-DIGOTA Using I/O Devices in FinFET Technology
2025 · Alexandra Matos, Ricardo Machado, et al. · IEEE Nordic Circuits and Systems Conference (NorCAS)
A Tunable Bandwidth and Center Frequency 6-Path BPF with Improved 3 $k^{th}$ Harmonics Rejection
2022 · Mounika Akula, Boyapati Subrahmanyam, et al. · Austrochip Workshop on Microelectronics (Austrochip)
0.18μm CMOS技術によるEMI耐性演算増幅器のモデリングと設計
2016 · Boyapati Subrahmanyam, Redoute Jean-Michel, et al. · IEEE Transactions on Electromagnetic Compatibility
0.18μm CMOS技術における高EMI免疫折畳みカスコード演算増幅器【Powered by NICT】
2016 · Subrahmanyam Boyapati, Redoute Jean-Michel, et al. · IEEE Conference Proceedings
Works count: 25
Citation count: 119
H-index: 7
I10-index: 6
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