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Kaori Tai

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process
2007 · J. Wang, Y. Tateshita, et al. · Symposium on VLSI Technology · 28
High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates
2006 · Y. Tateshita, J. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24
High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates
2009 · Satoru Mayuzumi, Shinya Yamakawa, et al. · IEEE Transactions on Electron Devices · 23
Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates
2007 · S. Mayuzumi, J. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
A study for 0.18 /spl mu/m high-density MRAM
2004 · M. Motoyoshi, I. Yamamura, et al. · Symposium on VLSI Technology · 18
Microstructural study on the C49-to-C54 phase transformation in TiSi2 formed from preamorphization implantation
1999 · M. Okihara, N. Hirashita, et al. · Journal of Applied Physics · 12
Mechanism of Carrier Mobility Degradation Induced by Crystallization of HfO2Gate Dielectrics
2009 · Takashi Ando, Takayoshi Shimura, et al. · Applied Physics Express · 11
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Application of HfSiON to Deep-Trench Capacitors of Sub-45-nm-Node Embedded Dynamic Random-Access Memory
2006 · Takashi Ando, Naoyuki Sato, et al. · Japanese Journal of Applied Physics · 10
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High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology
2006 · S. Yamaguchi, K. Tai, et al. · Symposium on VLSI Technology · 9
Effect of preamorphization implantation on C54–TiSi2 formation in salicided narrow lines
1999 · Kaori Tai, Masao Okihara, et al. · Journal of Applied Physics · 9
Study on mechanism of crystallization in HfO2 films on Si substrates by in-depth profile analysis using photoemission spectroscopy
2009 · Satoshi Toyoda, Haruhiko Takahashi, et al. · Journal of Applied Physics · 7
Newly developed electro-chemical polishing process of copper as replacement of CMP suitable for damascene copper inlaid in fragile low-k dielectrics
2002 · S. Sato, Z. Yasuda, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Threshold Voltage Modulation Technique using Fluorine Treatment through Atomic Layer Deposition TiN Suitable for Complementary Metal–Oxide–Semiconductor Devices
2008 · Kaori Tai, Shinpei Yamaguchi, et al. · Japanese Journal of Applied Physics · 6
Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application
2006 · T. Ando, T. Hirano, et al. · Symposium on VLSI Technology · 5
High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process
2006 · K. Tai, T. Hirano, et al. · European Solid-State Device Research Conference · 4
Fragile porous low-k/copper integration by using electro-chemical polishing
2003 · S. Takahashi, K. Tai, et al. · Symposium on VLSI Technology · 4
Low Threshold Voltage and High Mobility N-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using Hf–Si/HfO2Gate Stack Fabricated by Gate-Last Process
2010 · Takashi Ando, Tomoyuki Hirano, et al. · Japanese Journal of Applied Physics · 3
Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone–Water-Last Treatment
2008 · Itaru Oshiyama, Kaori Tai, et al. · Japanese Journal of Applied Physics · 3
Transmission Electron Microscopic Studies of TiSi2 Microstructures and the C49-C54 Phase Transformation in Narrow Lines
1999 · Masao Okihara, Kaori Tai, et al. · Japanese Journal of Applied Physics · 3
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High performance nMOSFET with HfSi/subx//HfO/sub 2/ gate stack by low temperature process
2006 · T. Hirano, T. Ando, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Band-Edge High-Performance Metal-Gate/High-$\kappa$ nMOSFET Using $\hbox{Hf}{-}\hbox{Si}/\hbox{HfO}_{2}$ Stack
2009 · Takashi Ando, Tomoyuki Hirano, et al. · IEEE Transactions on Electron Devices · 1
New complementary PVD-Ta/CVD-WN stacked barrier structure for copper metallization
2003 · Kaori Tai, H. Ohtorii, et al. · IEEE International Interconnect Technology Conference (IITC) · 1
Application of HfSiON to Deep Trench Capacitors of Sub-45nm Node Embedded DRAM
2007 · T. Ando, N. Sato, et al. · International Conference on Solid State Devices and Materials (SSDM)
Tinv Scaling and Jg Reducing for nMOSFET with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone Water Treatment Process
2007 · I. Oshiyama, K. Tai, et al. · International Conference on Solid State Devices and Materials (SSDM)
PMOSFET Vth Modulation Technique using Fluorine Treatment through ALD-TiN Suitable for CMOS Devices
2007 · K. Tai, S. Yamaguchi, et al. · International Conference on Solid State Devices and Materials (SSDM)
Works count: 28
Citation count: 208
H-index: 9
I10-index: 8
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