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Iris Xu

OpenAlex ID: A5043526217
Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging
2018 · John H. Lau, Ming Li, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 101
Fan-Out Wafer-Level Packaging for Heterogeneous Integration
2018 · John H. Lau, Ming Li, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 95
Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers
2018 · John H. Lau, Ming Li, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 59
Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration
2018 · Cheng-Ta Ko, Henry Yang, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 55
Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)
2017 · John Lau, Ming Li, et al. · Journal of Microelectronics and Electronic Packaging · 42
Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration
2018 · Cheng-Ta Ko, Chieh-Lin Chang, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 36
Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration
2018 · Cheng-Ta Ko, Henry Yang, et al. · Journal of Microelectronics and Electronic Packaging · 31
Reliability of Fan-Out Wafer-Level Heterogeneous Integration
2018 · John Lau, Ming Li, et al. · Journal of Microelectronics and Electronic Packaging · 26
Fan-Out Wafer-Level Packaging for Heterogeneous Integration
2018 · John Lau, Zhang Li, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 24
Reliability of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Re-Distributed Layers
2018 · John Lau, Eric Kuah, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 19
Characterizations of Fan-out Wafer-Level Packaging
2017 · Ming Li, Qingqian Li, et al. · IMAPSource Proceedings · 11
Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)
2017 · John Lau, Ming Li, et al. · IMAPSource Proceedings · 10
Feasibility Study of Fan-Out Panel-Level Packaging for Heterogeneous Integrations
2019 · Cheng-Ta Ko, Henry Yang, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 8
Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Redistributed Layers
2018 · John Lau, Wu Kai, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 6
Feasibility Study of Fan-Out Wafer-Level Packaging for Heterogeneous Integrations
2019 · John Lau, Ming Li, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 5
Reliability of Fan-Out Wafer-Level Heterogeneous Integration
2018 · John Lau, Ming Li, et al. · IMAPSource Proceedings · 4
Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration
2018 · Cheng-Ta Ko, Henry Yang, et al. · IMAPSource Proceedings · 3
Security on Networks
2013 · Bonny Jain, John Wang, et al.
Works count: 18
Citation count: 535
H-index: 11
I10-index: 12
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