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Ming‐Dou Ker

Observed names: Ker, Ming-Dou, M. D. Ker, M. Ker, M.-D. KER, M.-D. Ker, M.D. Ker, Ming Dou Ker, Ming-Dou KER, Ming-Dou Ker, Ming-dou Ker
Observed institutions: ITRI International, National Yang Ming Chiao Tung University, Winbond (Taiwan), Institute of Electrical and Electronics Engineers, Institute of Electronics, Information and Communication Engineers, Taiwan Semiconductor Manufacturing Company (Taiwan), Industrial Technology Research Institute, I-Shou University, KU Leuven
ORCID: 0000-0003-3622-181X
Observed ORCID: 0000-0003-3622-181X
OpenAlex ID: A5043540734
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
1999 · Ming-Dou Ker · IEEE Transactions on Electron Devices · 312
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
2013 · Wei-Ming Chen, Herming Chiueh, et al. · IEEE Journal of Solid-State Circuits · 282
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
2005 · Ming-Dou Ker, K.-C. Hsu · IEEE Transactions on Device and Materials Reliability · 253
Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes
2006 · M.-D. Ker, S.-L. Chen, et al. · IEEE Journal of Solid-State Circuits · 218
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
2018 · Cheng-Hsiang Cheng, Ping-Yuan Tsai, et al. · IEEE Journal of Solid-State Circuits · 148
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation
2006 · M.-D. Ker, J.-S. Chen · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 112
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process
2016 · Zhicong Luo, Ming-Dou Ker · IEEE Transactions on Biomedical Circuits and Systems · 89
Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices
2001 · Tung-Yang Chen, Ming-Dou Ker · IEEE Transactions on Device and Materials Reliability · 89
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs
1997 · Ming-Dou Ker, Hun-Hsien Chang, et al. · IEEE Journal of Solid-State Circuits · 74
Transient‐Induced Latchup in CMOS Integrated Circuits
2009 · Ming‐Dou Ker, Sheng‐Fu Hsu · Wiley eBooks · 72
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
2011 · Ming-Dou Ker, Chun-Yu Lin, et al. · IEEE Transactions on Device and Materials Reliability · 68
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
1996 · Ming-Dou Ker, Chung-Yu Wu, et al. · IEEE Transactions on Electron Devices · 66
Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology
2003 · Ming-Dou Ker, Wen-Yu Lo · IEEE Transactions on Semiconductor Manufacturing · 64
Physical Mechanism and Device Simulation on Transient-Induced Latchup in CMOS ICs Under System-Level ESD Test
2005 · M.-D. Ker, S.-F. Hsu · IEEE Transactions on Electron Devices · 60
A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals
2005 · Shih-Lun Chen, Ming-Dou Ker · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 60
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
2000 · Ming-Dou Ker, Tung-Yang Chen, et al. · IEEE Journal of Solid-State Circuits · 60
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
1996 · Ming-Dou Ker, Chung-Yu Wu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 58
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
2008 · Ming-Dou Ker, Cheng-Cheng Yen · IEEE Journal of Solid-State Circuits · 56
Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations
2006 · M.-D. Ker, S.-F. Hsu · IEEE Transactions on Device and Materials Reliability · 55
Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors
2006 · M.-D. Ker, S.-L. Chen, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 54
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process
2017 · Zhicong Luo, Ming-Dou Ker, et al. · IEEE Transactions on Biomedical Circuits and Systems · 53
Latchup-free esd protection design with complementary substrate-triggered scr devices
2003 · Ming-Dou Ker, Kuo-Chun Hsu · IEEE Journal of Solid-State Circuits · 51
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS process
2000 · Ming-Dou Ker, Wen-Yu Lo · IEEE Journal of Solid-State Circuits · 51
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
2011 · Wen-Yi Chen, Elyse Rosenbaum, et al. · IEEE Transactions on Device and Materials Reliability · 50
ESD test methods on integrated circuits: an overview
2002 · Ming-Dou Ker, Jeng-Jie Peng, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 50
Works count: 667
Citation count: 8,395
H-index: 40
I10-index: 236
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