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Author

Takshashila Pathade

Observed institution: Dhirubhai Ambani University
ORCID: 0000-0001-9212-3785
Observed ORCID: 0000-0001-9212-3785
OpenAlex ID: A5044644251
Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
2021 · Takshashila Pathade, Yash Agrawal, et al. · IEEE Transactions on Nanotechnology · 31
Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects
2018 · Takshashila Pathade, Urmi Shah, et al. · IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) · 6
Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit
2023 · Gulafsha Bhatti, Takshashila Pathade, et al. · IETE Journal of Research · 5
Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects
2021 · Takshashila Pathade, Yash Agrawal, et al. · Materials Today Proceedings · 5
CNTFET Based Low Power Repeaters for On-Chip Interconnect System
2021 · Takshashila Pathade, Yash Agrawal, et al. · International Symposium on VLSI Design and Test (VDAT) · 2
Effective Low Power ALU Design with Incorporation of MWCNTB On-chip Interconnects
2022 · Takshashila Pathade, Yash Agrawal, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 1
Prospective Incorporation of Booster in Carbon Interconnects for High-Speed Integrated Circuits
2020 · Takshashila Pathade, Yash Agrawal, et al. · Lecture notes in electrical engineering · 1
Variability Analysis of Carbon Nanotube-Based Driver-Interconnect-Load Model for ICs
2026 · Takshashila Pathade, Yash Agrawal, et al. · Springer eBooks
Accurate FDTD-Based Modeling with Practical CMOS Inverter Consideration for Driver and Load in On-Chip Interconnect System
2026 · Takshashila Pathade, Yash Agrawal, et al. · Lecture notes in electrical engineering
Works count: 9
Citation count: 51
H-index: 4
I10-index: 1
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