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Francesco Menichelli
Observed names:
F. MENICHELLI,
F. Menichelli,
MENICHELLI, FRANCESCO,
Menichelli F.
Institutions:
Fondazione ICSC Centro Nazionale di Ricerca in High Performance Computing, Big Data e Quantum Computing,
Sapienza University of Rome
Observed institutions:
Fondazione ICSC Centro Nazionale di Ricerca in High Performance Computing, Big Data e Quantum Computing,
Sapienza University of Rome
ORCID:
0000-0002-8453-6536
Observed ORCID:
0000-0002-8453-6536
OpenAlex ID:
A5045257843
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
2005
·
Luca Benini
, Davide Bertozzi
, et al.
·
The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology
·
249
A post-compiler approach to scratchpad mapping of code
2004
·
Federico Angiolini
, Francesco Menichelli
, et al.
·
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
·
102
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips
2008
·
F. Menichelli
, R. Menicocci
, et al.
·
IEEE Transactions on Dependable and Secure Computing
·
31
A class of code compression schemes for reducing power consumption in embedded microprocessor systems
2004
·
L. Benini
, F. Menichelli
, et al.
·
IEEE Transactions on Computers
·
29
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
2022
·
Marcello Barbirotta
, Abdallah Cheikh
, et al.
·
Journal of Low Power Electronics and Applications
·
28
PDF
Side Channel Analysis Resistant Design Flow
2006
·
M. Aigner
, S. Mangard
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
27
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems
2024
·
Marcello Barbirotta
, Francesco Menichelli
, et al.
·
IEEE Access
·
25
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
2020
·
Marcello Barbirotta
, Antonio Mastrandrea
, et al.
·
Proceedings
·
24
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors
2022
·
Marcello Barbirotta
, Abdallah Cheikh
, et al.
·
IEEE Access
·
22
PDF
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores
2017
·
Mauro Olivieri
, Abdallah Cheikh
, et al.
·
IEEE International Conference on New Generation of Circuits and Systems (NGCAS)
·
20
Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes
2023
·
Marcello Barbirotta
, Abdallah Cheikh
, et al.
·
Electronics
·
19
PDF
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips
2009
·
F. Menichelli
, M. Olivieri
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
19
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
2021
·
Marcello Barbirotta
, Abdallah Cheikh
, et al.
·
Proceedings
·
16
Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 Implementation
2021
·
Mauro Olivieri
, Abdallah Cheikh
, et al.
·
Electronics
·
14
PDF
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
2020
·
Abdallah Cheikh
, Stefano Sordillo
, et al.
·
Lecture notes in electrical engineering
·
14
Testing power-analysis attack susceptibility in register-transfer level designs
2007
·
M. Bucci
, R. Luzzi
, et al.
·
IET Information Security
·
14
Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder
2018
·
Giulia Stazi
, Lorenzo Adani
, et al.
·
Lecture notes in computer science
·
13
PDF
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer
2020
·
Luigi Blasi
, Francesco Vigli
, et al.
·
Lecture notes in electrical engineering
·
12
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
2024
·
Marco Angioli
, Marcello Barbirotta
, et al.
·
IEEE Transactions on Computers
·
11
PDF
A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection
2024
·
Francesco Vigli
, Marcello Barbirotta
, et al.
·
IEEE Access
·
11
PDF
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration
2022
·
Marcello Barbirotta
, Abdallah Cheikh
, et al.
·
Conference on Ph.D. Research in Microelectronics and Electronics
·
11
Introducing approximate memory support in Linux Kernel
2017
·
Giulia Stazi
, Francesco Menichelli
, et al.
·
Conference on Ph.D. Research in Microelectronics and Electronics
·
10
Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks
2012
·
Claudio S. Malavenda
, F. Menichelli
, et al.
·
Journal of Computer Networks and Communications
·
8
PDF
A delay model allowing nano-CMOS standard cells statistical simulation at the logic level
2011
·
Antonio Mastrandrea
, Francesco Menichelli
, et al.
·
Conference on Ph.D. Research in Microelectronics and Electronics
·
8
A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design
2004
·
Francesco Menichelli
, Mauro Olivieri
, et al.
·
Design, Automation, and Test in Europe
·
8
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Works count:
77
Citation count:
842
H-index:
14
I10-index:
22
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