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Sherif M. Sharroush

Observed names: S. M. Sharroush, Sherif Sharroush, Sherif M. Sharroush
ORCID: 0000-0001-7911-2571
Observed ORCID: 0000-0001-7911-2571
OpenAlex ID: A5047023966
Subthreshold MOSFET transistor amplifier operation
2009 · Sherif M. Sharroush, Yasser S. Abdalla, et al. · International Design and Test Workshop (IDT) · 31
Analysis of the subthreshold CMOS logic inverter
2016 · Sherif M. Sharroush · Ain Shams Engineering Journal · 28
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A voltage-controlled ring oscillator based on an FGMOS transistor
2017 · Sherif M. Sharroush · Microelectronics Journal · 27
Design of the CMOS inverter‐based amplifier: A quantitative approach
2019 · Sherif M. Sharroush · International Journal of Circuit Theory and Applications · 25
Impact of technology scaling on the performance of domino CMOS logic
2008 · Sherif M. Sharroush, Yasser S. Abdalla, et al. · International Conference on Electronic Design · 19
Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper
2008 · Sherif M. Sharroush, Yasser S. Abdalla, et al. · International Conference on Computer and Communication Engineering · 12
Dynamic random-access memories without sense amplifiers
2012 · S. M. Sharroush, Y. S. Abdalla, et al. · e+i Elektrotechnik und Informationstechnik · 11
Performance optimization of MOS current-mode logic
2016 · Sherif M. Sharroush · International Conference on Electrical, Electronics, and Optimization Techniques · 9
A predischarged bitline 1T-1C DRAM readout scheme
2018 · Sherif M. Sharroush · Microelectronics Journal · 7
Impact of technology scaling on the performance of DRAMs
2016 · Sherif M. Sharroush · International Conference on Electronic Devices, Systems and Applications · 7
Reading DRAM cells using two properly designed cascaded inverters
2014 · Sherif M. Sharroush · e+i Elektrotechnik und Informationstechnik · 7
A novel low-power and high-speed dynamic CMOS logic circuit technique
2009 · Sherif M. Sharroush, Yasser S. Abdalla, et al. · 7
Parameter extraction and modelling of the MOS transistor by an equivalent resistance
2021 · Sherif M. Sharroush, Yasser S. Abdalla · Mathematical and Computer Modelling of Dynamical Systems · 6
Understanding the behavior of RTD-loaded NMOS inverter through compact-form analysis
2017 · Sherif M. Sharroush · Ain Shams Engineering Journal · 6
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A novel variable-gain amplifier based on an FGMOS transistor
2016 · Sherif M. Sharroush · International Conference on Electronic Devices, Systems and Applications · 6
Compensating for the keeper current of CMOS domino logic using a well designed NMOS transistor
2009 · Sherif M. Sharroush, Yasser S. Abdalla, et al. · 6
Inverter‐based voltage‐controlled and programmable comparators
2020 · Sherif M. Sharroush · International Journal of Circuit Theory and Applications · 5
Time-Domain Readout of 1T–1C DRAM Cells
2017 · Sherif M. Sharroush · Journal of Circuits Systems and Computers · 5
Representing the transistor by an equivalent resistor
2016 · Sherif M. Sharroush · International Conference on Electronic Devices, Systems and Applications · 5
A bitline-driven 1T-1C DRAM readout scheme
2016 · Sherif M. Sharroush · International Conference on Electrical, Electronics, and Optimization Techniques · 5
Optimum sizing of the sleep transistor in MTCMOS technology
2021 · Sherif M. Sharroush, Yasser S. Abdalla · AEU - International Journal of Electronics and Communications · 4
A novel low-latency DRAM based on the bitline-discharge rate
2018 · Sherif M. Sharroush · International Journal of Electronics · 4
A novel high-performance time-balanced wide fan-in CMOS circuit
2016 · Sherif M. Sharroush · Alexandria Engineering Journal · 4
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Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element
2024 · Sherif M. Sharroush, Yasser S. Abdalla · Integration · 3
Two proposed BiCMOS inverters with enhanced performance
2023 · Sherif M. Sharroush, Yasser S. Abdalla · Ain Shams Engineering Journal · 3
Works count: 53
Citation count: 284
H-index: 8
I10-index: 7
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