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Genaro Mariniello

Hot carrier degradation in nanowire transistors: Physical mechanisms, width dependence and impact of Self-Heating
2016 · A. Laurent, X. Garros, et al. · Symposium on VLSI Technology · 22
Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
2012 · Genaro Mariniello, Rodrigo Trevisoli Doria, et al. · International Caribbean Conference on Devices, Circuits and Systems · 16
Experimental Analysis of Self-Heating Effects Using the Pulsed IV Method in Junctionless Nanowire Transistors
2018 · Flavio Enrico Bergamaschi, Genaro Mariniello, et al. · Symposium on Microelectronics Technology and Devices · 10
Underestimation of measured self‐heating in nanowires by using gate resistance technique
2016 · G. Mariniello, M. Cassé, et al. · Electronics Letters · 10
A simulation study of self-heating effect on junctionless nanowire transistors
2014 · G. Mariniello, M. A. Pavanello · Symposium on Microelectronics Technology and Devices · 7
Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K
2022 · Genaro Mariniello, Sylvain Barraud, et al. · Solid-State Electronics · 6
Electrical characterization of stacked SOI nanowires at low temperatures
2022 · Jaime C. Rodrigues, Genaro Mariniello, et al. · Solid-State Electronics · 6
Analog characteristics of n-type vertically stacked nanowires
2021 · Genaro Mariniello, Cesar Augusto Belchior de Carvalho, et al. · Solid-State Electronics · 5
Self-heating-based analysis of gate structures on junctionless nanowire transistors
2017 · F. E. Bergamaschi, M. A. Pavanello, et al. · Symposium on Microelectronics Technology and Devices · 4
Analysis of charges densities in multiple-gates SOI nMOS junctionless
2013 · G. Mariniello, A. Cerdeira, et al. · Symposium on Microelectronics Technology and Devices · 4
Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs
2021 · Jaime C. Rodrigues, Genaro Mariniello, et al. · Symposium on Microelectronics Technology and Devices · 3
Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires
2020 · Genaro Mariniello, Sylvain Barraud, et al. · Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon · 2
An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires
2022 · Michelly de Souza, Jaime Calcade Rodrigues, et al. · IEEE Workshop on Low Temperature Electronics (WOLTE) · 1
Simulation Comparison of Self-Heating Effects in Junctionless Nanowire Transistors and FinFET Devices
2015 · Genaro Mariniello, Marcelo Pavanello · ECS Meeting Abstracts · 1
Simulation Comparison of Self-Heating Effects in Junctionless Nanowire Transistors and FinFET Devices
2015 · Genaro Mariniello, Marcelo Pavanello · ECS Transactions · 1
Intrinsic Gate Capacitances of n-type Junctionless Nanowire Transistors Using a Three-Dimensional Device Simulation and Experimental Measurements
2012 · G. Mariniello, R. T. Doria, et al. · ECS Transactions · 1
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Performance of Stacked SOI Nanowires in a Wide Temperature Range
2021 · Jaime C. Rodrigues, Genaro Mariniello, et al. · Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
Aumento de eficiência na captação energética de árvores solares
2019 · Hélvio Henrique Rodrigues, Rogério Luis Spagnolo da Silva, et al. · Simpósio Brasileiro de Tecnologia da Informação e Comunicação na Construção
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Works count: 18
Citation count: 99
H-index: 6
I10-index: 4
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