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C. Hora
Observed name:
C Hora
Institutions:
NXP (Netherlands),
Politehnica University of Timisoara
Observed institutions:
NXP (Netherlands),
Politehnica University of Timisoara,
Philips (Netherlands),
NXP (Germany),
Signify (Netherlands),
Eindhoven University of Technology
show all 6
OpenAlex ID:
A5055122093
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs
2009
·
F. Hapke
, R. Krenz-Baath
, et al.
·
IEEE International Test Conference (ITC)
·
95
Systematic defects in deep sub-micron technologies
2005
·
B. Kruseman
, A. Majhi
, et al.
·
IEEE International Test Conference (ITC)
·
69
An effective diagnosis method to support yield improvement
2003
·
C. Hora
, R. Segers
, et al.
·
IEEE International Test Conference (ITC)
·
65
Diagnosis of Local Spot Defects in Analog Circuits
2012
·
Ke Huang
, H. G. Stratigopoulos
, et al.
·
IEEE Transactions on Instrumentation and Measurement
·
58
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality
2008
·
S. Eichenberger
, J. Geuzebroek
, et al.
·
IEEE International Test Conference (ITC)
·
43
A novel stuck-at based method for transistor stuck-open fault diagnosis
2006
·
Xinyue Fan
, W. Moore
, et al.
·
IEEE International Test Conference (ITC)
·
38
Trends in testing integrated circuits
2005
·
B. Vermeulen
, C. Hora
, et al.
·
IEEE International Test Conference (ITC)
·
34
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis
2006
·
Xinyue Fan
, W. Moore
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
32
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example
2011
·
H Hashempour
, J Dohmen
, et al.
·
Design, Automation, and Test in Europe
·
27
Diagnosis of Full Open Defects in Interconnecting Lines
2007
·
R. Rodriguez-Montanes
, D. Arumi
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
26
Medical data mining with extended WEKA
2012
·
R. Robu
, C. Hora
·
IEEE International Conference on Intelligent Engineering Systems (INES)
·
17
Extending gate-level diagnosis tools to CMOS intra-gate faults
2007
·
X. Fan
, W.R. Moore
, et al.
·
IET Computers & Digital Techniques
·
17
Stuck-Open Fault Diagnosis with Stuck-At Model
2005
·
Xinyue Fan
, W. Moore
, et al.
·
IEEE European Test Symposium (ETS)
·
17
Impact of gate tunnelling leakage on CMOS circuits with full open defects
2007
·
R. Rodríguez-Montañés
, D. Arumí
, et al.
·
Electronics Letters
·
12
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages
2007
·
D. Arumi
, R. Rodriguez-Montanes
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
9
I DDQ -based diagnosis at very low voltage (VLV) for bridging defects
2007
·
D. Arumi
, R. Rodríguez-Montañés
, et al.
·
Electronics Letters
·
9
Diagnosis of full open defects in interconnect lines with fan-out
2010
·
R. Rodriguez-Montanes
, D. Arumi
, et al.
·
IEEE European Test Symposium (ETS)
·
8
Time-dependent Behaviour of Full Open Defects in Interconnect Lines
2008
·
R. Rodriguez-Montanes
, D. Arumi
, et al.
·
IEEE International Test Conference (ITC)
·
6
Improving diagnostic resolution of delay faults using path delay fault model
2003
·
A.K. Majhi
, G. Gronthoud
, et al.
·
IEEE VLSI Test Symposium (VTS)
·
6
VTS 2007 Best Paper Award
2007
·
Adit D. Singh
, Magdy S. Abadir
, et al.
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Works count:
20
Citation count:
588
H-index:
13
I10-index:
14
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