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Goutham Arutchelvan

Observed names: Arutchelvan, Goutham, G. Arutchelvan
ORCID: 0000-0003-1535-0663
Observed ORCID: 0000-0003-1535-0663
OpenAlex ID: A5055896171
2D materials: roadmap to CMOS integration
2018 · C. Huyghebaert, T. Schram, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 102
Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain current
2019 · Quentin Smets, Goutham Arutchelvan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 92
Impact of device scaling on the electrical properties of MoS2 field-effect transistors
2021 · Goutham Arutchelvan, Quentin Smets, et al. · Scientific Reports · 89
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From the metal to the channel: a study of carrier injection through the metal/2D MoS 2 interface
2017 · Goutham Arutchelvan, César J. Lockhart de la Rosa, et al. · Nanoscale · 69
Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab
2020 · I. Asselberghs, Q. Smets, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 65
Reactive plasma cleaning and restoration of transition metal dichalcogenide monolayers
2021 · Daniil Marinov, Jean-François de Marneffe, et al. · npj 2D Materials and Applications · 62
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Introducing 2D-FETs in Device Scaling Roadmap using DTCO
2020 · Z. Ahmed, A. Afzalian, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 51
Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
2020 · Anshul Gupta, Olalla Varela Pedreira, et al. · IEEE Transactions on Electron Devices · 42
MoS2 Functionalization with a Sub-nm Thin SiO2 Layer for Atomic Layer Deposition of High-κ Dielectrics
2017 · Haodong Zhang, Goutham Arutchelvan, et al. · Chemistry of Materials · 42
Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster
2021 · A. Veloso, Anne Jourdain, et al. · Symposium on VLSI Technology · 30
Monolayer-MoS 2 Stacked Nanosheet Channel with C-type Metal Contact
2023 · Yun-Yan Chung, Wei-Sheng Yun, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 29
Graphene based Van der Waals contacts on MoS 2 field effect transistors
2020 · Vivek Mootheri, Goutham Arutchelvan, et al. · 2D Materials · 29
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Insight on the Characterization of MoS2Based Devices and Requirements for Logic Device Integration
2016 · César J. Lockhart de la Rosa, Goutham Arutchelvan, et al. · ECS Journal of Solid State Science and Technology · 29
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Sources of variability in scaled MoS2 FETs
2020 · Quentin Smets, Devin Verreck, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28
Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
2023 · Ang-Sheng Chou, Ching-Hao Hsu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
2022 · A. Veloso, A. Jourdain, et al. · IEEE Transactions on Electron Devices · 25
The Role of Nonidealities in the Scaling of MoS2 FETs
2018 · Devin Verreck, Goutham Arutchelvan, et al. · IEEE Transactions on Electron Devices · 22
Scaled contact length with low contact resistance in monolayer 2D channel transistors
2023 · Wen-Chia Wu, Terry Y.T. Hung, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 20
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
2020 · A. Gupta, H. Mertens, et al. · Symposium on VLSI Technology · 19
Enhancement-Mode Atomic Layer Deposited W-Doped In2O3 Transistor at 55 nm Channel Length by Oxide Capping Layer with Improved Stability
2024 · Qing Lin, Nathaniel Safron, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 16
Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS 2 Channel Transistors
2023 · Wen-Chia Wu, Terry Y. T. Hung, et al. · IEEE Transactions on Electron Devices · 13
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
2022 · A. Veloso, A. Jourdain, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 13
Relation between film thickness and surface doping of MoS2 based field effect transistors
2018 · César J. Lockhart de la Rosa, Goutham Arutchelvan, et al. · APL Materials · 12
Transport properties of chemically synthesized MoS2 – Dielectric effects and defects scattering
2016 · Massimo Mongillo, Daniele Chiappe, et al. · Applied Physics Letters · 12
Low-Power CMOS Inverter with Enhancement-Mode Operation and Matched $\mathrm{V}_{\text{TH}}$ at $\mathrm{V}_{\text{DD}} =1\ \mathrm{V}$ on Monolayer 2D Material Channel
2024 · Ang-Sheng Chou, Ching-Hao Hsu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Works count: 48
Citation count: 990
H-index: 19
I10-index: 24
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