Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
Year: 2022
Type: conference-paper
Authors: A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, K. Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, T. Schram, B. Briggs, C. Lorant, E. Rosseel, A. Hikavyy, R. Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, K. Devriendt, B. T. Chan, S. Demuynck, G. Hiblot, G. Van der Plas, J. Ryckaert, G. Beyer, E. Dentoni Litta, E. Beyne, N. Horiguchi
Institution: IMEC
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4286571708