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Boon Teik Chan

Observed names: B. T. Chan, B.T. Chan, Chan, Boon Teik
Institution: IMEC
ORCID: 0000-0003-2890-0388
Observed ORCID: 0000-0003-2890-0388
OpenAlex ID: A5000465847
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
2020 · S. Subramanian, M. Hosseini, et al. · Symposium on VLSI Technology · 144
Implementation of templated DSA for via layer patterning at the 7nm node
2015 · Roel Gronheid, Jan Doise, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 117
A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$-Based 1T1R CBRAM Cell
2013 · Attilio Belmonte, Woosik Kim, et al. · IEEE Transactions on Electron Devices · 88
Area-Selective Atomic Layer Deposition of TiN, TiO2, and HfO2 on Silicon Nitride with inhibition on Amorphous Carbon
2018 · Eric Stevens, Yoann Tomczak, et al. · Chemistry of Materials · 82
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
2023 · H. Mertens, M. Hosseini, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 73
Insight into Selective Surface Reactions of Dimethylamino-trimethylsilane for Area-Selective Deposition of Metal, Nitride, and Oxide
2020 · Job Soethoudt, Yoann Tomczak, et al. · The Journal of Physical Chemistry C · 59
CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling
2023 · Hsiao-Hsuan Liu, Shairfe M. Salahuddin, et al. · IEEE Transactions on Electron Devices · 55
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Defect reduction and defect stability in IMEC's 14nm half-pitch chemo-epitaxy DSA flow
2014 · Roel Gronheid, Paulina Rincon Delgadillo, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 54
Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
2021 · R. Ritzenthaler, H. Mertens, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 45
Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
2020 · Anshul Gupta, Olalla Varela Pedreira, et al. · IEEE Transactions on Electron Devices · 42
Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow
2015 · Hari Pathangi, Boon Teik Chan, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 40
CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
2023 · Hsiao-Hsuan Liu, Pieter Schuddinck, et al. · IEEE Transactions on Electron Devices · 38
Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures
2022 · H. Mertens, R. Ritzenthaler, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 36
Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster
2021 · A. Veloso, Anne Jourdain, et al. · Symposium on VLSI Technology · 30
Conversion of a Patterned Organic Resist into a High Performance Inorganic Hard Mask for High Resolution Pattern Transfer
2018 · Jean-François de Marneffe, Boon Teik Chan, et al. · ACS Nano · 26
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
2022 · A. Veloso, A. Jourdain, et al. · IEEE Transactions on Electron Devices · 25
Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts
2024 · S. Demuynck, V. Vega Gonzalez, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 24
Rectification of EUV-patterned contact holes using directed self-assembly
2013 · Roel Gronheid, Arjun Singh, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 24
Monolithic-CFET with Direct Backside Contact to Source/Drain and Backside Dielectric Isolation
2024 · A. Vandooren, K. Stiers, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23
28 nm pitch of line/space pattern transfer into silicon substrates with chemo-epitaxy Directed Self-Assembly (DSA) process flow
2014 · Boon Teik Chan, Shigeru Tahara, et al. · Microelectronic Engineering · 23
Defect Mitigation in Area‐Selective Atomic Layer Deposition of Ruthenium on Titanium Nitride/Dielectric Nanopatterns
2019 · Job Soethoudt, Hubert Hody, et al. · Advanced Materials Interfaces · 22
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Progress in directed self-assembly hole shrink applications
2013 · Todd R. Younkin, Roel Gronheid, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 22
3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
2020 · A. Vandooren, Z. Wu, et al. · Symposium on VLSI Technology · 21
Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space
2021 · Hans Mertens, R. Ritzenthaler, et al. · Symposium on VLSI Technology · 20
Implementation of surface energy modification in graphoepitaxy directed self-assembly for hole multiplication
2015 · Jan Doise, Joost Bekaert, et al. · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 20
Works count: 76
Citation count: 1,476
H-index: 22
I10-index: 39
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