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Yeh-Ning Jou

Back-gate forward bias method for low-voltage CMOS digital circuits
1996 · Ming-Jer Chen, Jih-Shin Ho, et al. · IEEE Transactions on Electron Devices · 44
Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure
2009 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 27
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection
2022 · Jian-Hsing Lee, Yeh-Jen Huang, et al. · IEEE International Reliability Physics Symposium proceedings · 19
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration
2008 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 15
Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
2009 · Wen-Yi Chen, Ming-Dou Ker, et al. · IEEE International Symposium on Circuits and Systems proceedings · 12
RESURF Region Variation Induced Current Crowding Effect on HV p-LDMOS
2023 · Jian-Hsing Lee, Ching-Ho Li, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 9
The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit
2024 · Jian-Hsing Lee, Yeh-Jen Huang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 7
Unipolar Arc Ignited Partial Discharge for 650-V AlGaN/GaN HEMTs during the DC Breakdown Voltage Measurement
2022 · Jian-Hsing Lee, Chih-Cherng Liao, et al. · Energies · 7
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ESD Protection for Poly Fuses
2019 · Shao-Chang Huang, Jian-Hsing Lee, et al. · Annual EOS/ESD Symposium (EOS/ESD) · 6
Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology
2018 · Chia-Tsen Dai, Ming-Dou Ker, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 6
A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event
2023 · Jian-Hsing Lee, Ching-Ho Li, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 5
Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity
2015 · Kai-Neng Tang, Seian-Feng Liao, et al. · Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC) · 5
ESD simulation on GGNMOS for 40V BCD
2010 · Aloysius Priartanto Herlambang, Gene Sheu, et al. · IEEE Region 10 Conference (TENCON) · 5
A compact model of holding voltage for latch-up in epitaxial CMOS
2002 · Ming-Jer Chen, Chin-Shan Hou, et al. · IEEE International Reliability Physics Symposium proceedings · 5
Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances
2019 · Shao-Chang Huang, Hsien-Feng Liao, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) · 4
The Failure Mechanism of the Guard-Rings in Two Different Power Domains during the Latch-Up Test
2022 · Jian-Hsing Lee, Chih-Hsuan Lin, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 3
An Area-Saving and Low-Leakage ESD Protection Circuit for 650V E-Mode GaN-HEMT
2025 · Jian-Hsing Lee, Yeh-Jen Huang, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 2
The Failure Mechanism of Internal Circuit During ESD Striking a Power to Another Power
2024 · Chih-Cherng Liao, Ching-Ho Li, et al. · IEEE Transactions on Device and Materials Reliability · 2
The Effect of the P-Substrate Connection on the HBM Robustness of P-type ESD Device
2024 · Jian-Hsing Lee, Chih-Cherng Liao, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 2
Gate Voltages Impacting on Latch-up Measurements
2022 · Shao-Chang Huang, Jian-Hsing Lee, et al. · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) · 2
Optimization on On-Chip Surge Protection Device for USB Type-C HV Pins
2020 · Ming-Chun Chen, Ming-Dou Ker, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 2
ESD protection design with latchup-free immunity in 120V SOI process
2015 · Yi-Jie Huang, Ming-Dou Ker, et al. · IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference · 2
Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process
2006 · Sheng-fu Hsu, Ming-dou Ker, et al. · IEEE International Reliability Physics Symposium proceedings · 2
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection
2015 · Seian-Feng Liao, Kai-Neng Tang, et al. · European Conference on Circuit Theory and Design · 1
A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
1998 · Ming-Jer Chen, Hun-Shung Lee, et al. · IEEE Electron Device Letters · 1
Works count: 33
Citation count: 195
H-index: 7
I10-index: 5
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