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Author

P. Nguyen

Observed name: Phu Nguyen Ngoc Thien
Institution: FPT University
ORCID: 0009-0008-6085-336X
Observed ORCID: 0009-0008-6085-336X
OpenAlex ID: A5061097768
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell
2003 · S. Thompson, N. Anand, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 258
MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology
2018 · O. Golonzka, J. -G. Alzate, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 162
A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
2002 · S. Tyagi, M. Alavi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 149
3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling
2020 · C. -Y. Huang, G. Dewey, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 143
A high performance 180 nm generation logic technology
2002 · S. Yang, S. Ahmed, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 90
High performance and low power transistors integrated in 65nm bulk CMOS technology
2005 · Z. Luo, A. Steegen, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 82
An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V
2002 · S. Thompson, M. Alavi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62
90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology
2004 · C.-H. Jan, J. Bielefeld, et al. · IEEE International Interconnect Technology Conference (IITC) · 17
A novel approach to dual damascene patterning
2003 · M. Hussein, S. Sivakumar, et al. · IEEE International Interconnect Technology Conference (IITC) · 9
A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications
1999 · B. Agarwala, M. Armacost, et al. · European Solid-State Device Research Conference · 7
A New Metallization Technology for Advanced Interconnects on Substrates
1987 · P. Nguyen, F. Bachner · IEEE Transactions on Components Hybrids and Manufacturing Technology · 4
LexiChem: Shared-Latent Alignment for Faithful Text-to-Molecule Generation in SELFIES Space
2026 · Khoa Minh Nguyen, Nam Van Hai Phan, et al. · Lecture notes in computer science
Works count: 12
Citation count: 983
H-index: 9
I10-index: 8
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