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M. Cassé

Observed names: Casse, Casse, M., Casse, Mikael, Cassé, M., Cassé, Mikaël, M Casse, M Cassé, M. CASSE, M. Case, M. Casse, M. Cassé, M., Cassé, Mickael CASSE, Mickael Casse, Mickaël Cassé, Mikael Casse, Mikael Cassé, Mikaël Casse, Mikaël Cassé
Observed institutions: Institut polytechnique de Grenoble, Centre National de la Recherche Scientifique, Universidade de São Paulo, Institut National des Sciences Appliquées de Toulouse, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, CEA Grenoble, Laboratoire National des Champs Magnétiques Intenses, STMicroelectronics (France), Direction de la Recherche Technologique, Institut de Microélectronique, Electromagnétisme et Photonique, Institut Néel, Laboratoire d'Électronique des Technologies de l'Information, Centre de Radiofréquences, Optique et Micro-nanoélectronique des Alpes, Université Grenoble Alpes
ORCID: 0000-0002-4934-2445
Observed ORCID: 0000-0002-4934-2445
OpenAlex ID: A5066815409
Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm
2012 · S. Barraud, M. Berthome, et al. · IEEE Electron Device Letters · 262
Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening
2019 · H. Bohuslavskyi, A. G. M. Jansen, et al. · IEEE Electron Device Letters · 161
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Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm
2012 · S. Barraud, R. Coquand, et al. · IEEE Electron Device Letters · 152
3DVLSI with CoolCube process: An alternative path to scaling
2015 · P. Batude, C. Fenouillet-Beranger, et al. · Symposium on VLSI Technology · 145
FDSOI devices with thin BOX and ground plane integration for 32nm node and below
2009 · C. Fenouillet-Beranger, S. Denorme, et al. · Solid-State Electronics · 138
Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters
2006 · M. Casse, L. Thevenod, et al. · IEEE Transactions on Electron Devices · 132
Bonded planar double-metal-gate NMOS transistors down to 10 nm
2005 · M. Vinet, T. Poiroux, et al. · IEEE Electron Device Letters · 131
7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing
2020 · S. Barraud, B. Previtali, et al. · Symposium on VLSI Technology · 113
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
2010 · O. Faynot, F. Andrieu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 104
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
2010 · F. Andrieu, O. Weber, et al. · Symposium on VLSI Technology · 103
3D Sequential Integration: Application-driven technological achievements and guidelines
2017 · P. Batude, L. Brunet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 79
Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K
2019 · K. Triantopoulos, M. Casse, et al. · IEEE Transactions on Electron Devices · 76
On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature
2020 · G. Ghibaudo, M. Aouad, et al. · Solid-State Electronics · 72
Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
2010 · C. Fenouillet-Beranger, O. Thomas, et al. · Symposium on VLSI Technology · 72
Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
2020 · B. Cardoso Paz, L. Le Guevel, et al. · Symposium on VLSI Technology · 71
Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications
2020 · Bruna Cardoso Paz, Mikael Casse, et al. · IEEE Transactions on Electron Devices · 69
Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width
2013 · Remi Coquand, Mikaël Casse, et al. · IEEE Transactions on Electron Devices · 69
Strained tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD
2012 · A. Villalon, C. Le Royer, et al. · Symposium on VLSI Technology · 68
New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI
2014 · C. Fenouillet-Beranger, B. Mathieu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62
Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width
2012 · R. Coquand, S. Barraud, et al. · Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon · 57
Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric
2003 · F. Lime, K. Oshima, et al. · Solid-State Electronics · 55
28nm Fully-depleted SOI technology: Cryogenic control electronics for quantum computing
2017 · H. Bohuslavskyi, S. Barraud, et al. · Silicon Nanoelectronics Workshop (SNW) · 54
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Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate
2010 · M. Cassé, K. Tachi, et al. · Applied Physics Letters · 53
Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets
2018 · S. Barraud, B. Previtali, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 49
Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing
2004 · M. Cassé, J. Pretet, et al. · Solid-State Electronics · 48
Works count: 364
Citation count: 5,114
H-index: 36
I10-index: 119
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