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Luís Guerra e Silva

Observed names: L. Guerra e Silva, L.G. e Silva, Luis E Silva, Luis Guerra e Silva, Luis Silva, Luís G. Silva
ORCID: 0000-0001-5761-0131
Observed ORCID: 0000-0001-5761-0131
OpenAlex ID: A5074463063
Algorithms for solving Boolean satisfiability in combinational circuits
1999 · Luís Guerra e Silva, L. Miguel Silveira, et al. · Design, Automation, and Test in Europe · 42
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Satisfiability models and algorithms for circuit delay computation
2002 · Luís Guerra e Silva, João Marques-Silva, et al. · ACM Transactions on Design Automation of Electronic Systems · 39
Realistic delay modeling in satisfiability-based timing analysis
2002 · L.G. e Silva, J.P. Marques Silva, et al. · IEEE International Symposium on Circuits and Systems proceedings · 21
Solving satisfiability in combinational circuits
2003 · J. Marques-Silva, L. Guerra e Silva · IEEE Design & Test of Computers · 19
Efficient Computation of the Worst-Delay Corner
2007 · Luis Guerra e Silva, L. Miguel Silveira, et al. · Design, Automation, and Test in Europe · 18
Solving satisfiability in combinational circuits with backtrack search and recursive learning
2003 · J.P. Marques-Silva, L. Guerra e Silva · Symposium on Integrated Circuits and Systems Design · 15
Efficient computation of the worst-delay corner
2007 · Luís Guerra e Silva, L. Miguel Silveira, et al. · Design, Automation, and Test in Europe · 14
TAU 2013 variation aware timing analysis contest
2013 · Debjit Sinha, Luis Guerra e Silva, et al. · International Symposium on Physical Design · 11
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
2023 · Fabio Pavanello, Cedric Marchand, et al. · IEEE European Test Symposium (ETS) · 7
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Effective Corner-Based Techniques for Variation-Aware IC Timing Verification
2009 · Luis Guerra e Silva, Joel Phillips, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 7
Variation-Aware, Library Compatible Delay Modeling Strategy
2006 · Luis E Silva, Zhenhai Zhu, et al. · IFIP International Conference on Very Large Scale Integration (VLSI-SoC) · 7
Speedpath analysis under parametric timing models
2010 · Luis Guerra e Silva, Joel R. Phillips, et al. · ACM/IEEE Design Automation Conference (DAC) · 1
CommGate: A Communal Residential Gateway
2008 · Rui Moreira, Jorge Mamede, et al. · IEEE Consumer Communications and Networking Conference · 1
Library Compatible Variational Delay Computation
2007 · Luis Guerra e Silva, Zhenhai Zhu, et al. · Springer eBooks · 1
Ad–hoc Workflows for Higher Education
2015 · David Martinho, Samuel Coelho, et al. · euroCRIS DSpace CRIS digital repository (The International Organisation for Research Information)
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Improving SAT Solver Efficiency Using a Multi-Core Approach.
2013 · Ricardo Marques, Luís Guerra e Silva, et al. · The Florida AI Research Society
Unifying functional and parametric timing verification
2012 · Luis Guerra e Silva · ACM Great Lakes Symposium on VLSI (GLSVLSI)
Handling intra-die variations in PSTA
2011 · Luis Guerra e Silva, L. Miguel Silveira · ACM Great Lakes Symposium on VLSI (GLSVLSI)
Grid-based statistical timing analysis.
2005 · Luís Guerra e Silva, L. Miguel Silveira · IADIS AC
Exploiting Optimality Conditions in Accurate Static Circuit Tuning
2003 · Chandu Visweswariah, Andrew R. Conn, et al. · Applied optimization
Works count: 20
Citation count: 203
H-index: 8
I10-index: 8
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