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Luc Pinzelli

Observed names: L. Pinzelli, Pinzelli, L.
Observed institution: STMicroelectronics (France)
OpenAlex ID: A5075195231
28nm FDSOI technology platform for high-speed low-voltage digital applications
2012 · N. Planes, O. Weber, et al. · Symposium on VLSI Technology · 504
A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications
2013 · F. Boeuf, S. Cremer, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 102
Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
2010 · C. Fenouillet-Beranger, O. Thomas, et al. · Symposium on VLSI Technology · 88
In situ electric field simulation in metal/insulator/metal capacitors
2006 · Nicolas Gaillard, Luc Pinzelli, et al. · Applied Physics Letters · 68
Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
2010 · C. Fenouillet-Beranger, P. Perreau, et al. · Solid-State Electronics · 65
Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
2009 · C. Fenouillet-Beranger, P. Perreau, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 61
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
2009 · C. Fenouillet-Beranger, P. Perreau, et al. · European Solid-State Device Research Conference · 33
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
2009 · C. Fenouillet-Beranger, P. Perreau, et al. · European Solid-State Circuits Conference (ESSCIRC) · 29
Three-dimensional 35 nF/mm/sup 2/ MIM capacitors integrated in BiCMOS technology
2005 · A. Bajolet, J.-C. Giraudin, et al. · European Solid-State Device Research Conference · 22
Back Illuminated Vertically Pinned Photodiode with in Depth Charge Storage
2024 · J. Michelot, F. Roy, et al. · IISS online library · 20
Cu surface treatment influence on Si adsorption properties of CuSiN self-aligned barriers for sub-65nm technology node
2006 · S. Chhun, L.G. Gosset, et al. · Microelectronic Engineering · 17
Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology
2012 · C. Fenouillet-Beranger, P. Perreau, et al. · Solid-State Electronics · 14
Challenges in CMOS‐based images
2013 · Francois Roy, A. Tournier, et al. · Physica status solidi. C, Conferences and critical reviews/Physica status solidi. C, Current topics in solid state physics · 13
Multigate MOSFET in a Bulk Technology by Integrating Polysilicon-Filled Trenches
2009 · B. Ramadout, Guo-Neng Lu, et al. · IEEE Electron Device Letters · 13
Challenges and opportunity in performance, variability and reliability in sub-45nm CMOS technologies
2011 · F. Arnaud, L. Pinzelli, et al. · Microelectronics Reliability · 9
Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased ground plane FDSOI high-k/metal gate technology
2011 · C. Fenouillet-Beranger, P. Perreau, et al. · European Solid-State Device Research Conference · 8
A solution for an ideal planar multi-gates process for ultimate CMOS?
2010 · S. Monfray, J.-L. Huguenin, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 8
Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications
2010 · J. L. Huguenin, S. Monfray, et al. · International Conference on Solid State Devices and Materials (SSDM) · 8
Dopant diffusion and activation induced by sub-melt laser anneal within the co-implanted p+ polycrystalline silicon gate used in CMOS technologies
2009 · A. Colin, P. Morin, et al. · Thin Solid Films · 6
Characterization of Heated Ion Implantation for non Amorphizing Conditions and Correlation with Kinetic Monte Carlo Simulations
2018 · Sylvain Joblot, Romain Duru, et al. · International Conference on Ion Implantation Technology · 5
Junction engineering for FDSOI technology speed/power enhancement
2013 · O. Weber, N. Planes, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 5
High-K dielectric deposition in 3D architectures: The case of Ta2O5 deposited with metal–organic precursor TBTDET
2007 · L. Pinzelli, M. Gros-Jean, et al. · Microelectronics Reliability · 4
UTBOX and ground plane combined with Al2O3 inserted in TiN gate for VT modulation in fully-depleted SOI CMOS transistors
2011 · C. Fenouillet-Beranger, P. Perreau, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
Improved colour separation for a backside illuminated image sensor with 1.4 µm pixel pitch
2024 · Jens Prima, Francois Roy, et al. · HAL
Effects of technological and geometrical parameters of a tri-gate MOSFET fabricated in a bulk technology
2010 · B. Ramadout, G.-N. Lu, et al. · IEEE International Nanoelectronics Conference
Works count: 29
Citation count: 1,168
H-index: 14
I10-index: 16
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