Get started
Author

Liyang Lai

Institution: Shantou University
ORCID: 0000-0003-1041-8980
Observed ORCID: 0000-0003-1041-8980
OpenAlex ID: A5080887026
Signature based diagnosis for logic BIST
2007 · Wu-Tung Cheng, Manish Sharma, et al. · IEEE International Test Conference (ITC) · 49
Signature Based Diagnosis for Logic BIST
2006 · Wu-tung Cheng, Manish Sharma, et al. · IEEE International Test Conference (ITC) · 43
Hardware efficient LBIST with complementary weights
2006 · Liyang Lai, J.H. Patel, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 24
Logic BIST with scan chain segmentation
2005 · Liyang Lai, J.H. Patel, et al. · IEEE International Test Conference (ITC) · 21
Detection and Diagnosis of Static Scan Cell Internal Defect
2008 · Ruifeng Guo, Liyang Lai, et al. · IEEE International Test Conference (ITC) · 19
Diagnosis and Layout Aware (DLA) Scan Chain Stitching
2014 · Jing Ye, Yu Huang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 18
Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System
2022 · Jingbo Hu, Guohao Dai, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 10
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns
2020 · Liyang Lai, Qiting Zhang, et al. · IEEE International Test Conference in Asia (ITC-Asia) · 9
Programmable Scan-Based Logic Built-In Self Test
2007 · Liyang Lai, Liyang Lai, et al. · Proceedings - Asian Test Symposium/Proceedings · 8
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
2007 · Jerzy Tyszer, Janusz Rajski, et al. · IEEE Design & Test of Computers · 8
Logic BIST using constrained scan cells
2004 · Liyang Lai, T. Rinderknecht, et al. · IEEE VLSI Test Symposium (VTS) · 7
GPGPU-Based ATPG System: Myth or Reality?
2018 · Liyang Lai, Kun-Han Tsai, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 4
Diagnosis and Layout Aware (DLA) scan chain stitching
2013 · Jing Ye, Yu Huang, et al. · IEEE International Test Conference (ITC) · 3
Parallel Static Learning Toward Heterogeneous Computing Architectures
2023 · Xiaoze Lin, Liyang Lai, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2
Scalable Parallel Static Learning
2021 · Xiaoze Lin, Liyang Lai, et al. · IEEE International Test Conference in Asia (ITC-Asia) · 2
Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree
2011 · Yu Huang, Wu-Tung Cheng, et al. · Proceedings - International Symposium for Testing and Failure Analysis · 2
STDF Memory Fail Datalog Standard
2009 · Ajay Khoche, Jay Katz, et al. · IEEE VLSI Test Symposium (VTS) · 2
A testability-driven technology mapping method for optimized test point insertion
2026 · Xiaoze Lin, Liyang Lai, et al. · Integration
An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems
2025 · Xiaoze Lin, Liyang Lai, et al. · Design, Automation, and Test in Europe
Sideway Scan, Solving the Achilles’ Heel of Scan-based Diagnosis
2024 · Liyang Lai, Zefan Lin, et al. · IEEE International Test Conference in Asia (ITC-Asia)
GPU-Based Concurrent Static Learning
2023 · Huaxiao Liang, Xiaoze Lin, et al. · IEEE International Test Conference (ITC)
Parallel Logic Simulation for Functional Test
2023 · Liyang Lai, Yuxin Yang, et al. · Journal of Computer-Aided Design & Computer Graphics
PDF
New techniques for logic built-in self-test
2005 · J.H. Patel, Liyang Lai
Works count: 24
Citation count: 239
H-index: 8
I10-index: 7
Year
Topic
Type