Work

Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Year: 2014

Type: article

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI: 10.1109/tvlsi.2014.2313563

Authors: Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Weipin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles Liu, Sam Pan

Institutions: Chinese Academy of Sciences, Institute of Computing Technology, University of Chinese Academy of Sciences, State Key Laboratory of Computer Architecture, Mentor Graphics (United States), Synopsys (United States), Taiwan Semiconductor Manufacturing Company (Taiwan)

Language: English

Topic: VLSI and Analog Circuit Testing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

Funder: National Natural Science Foundation of China

Awards: G235384188, G4525781969, G6496145672, G886741113

OpenAlex ID: W2002246747

FWCI: 2.328

Cites: 31

Cited by: 18

Related to: 10