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Hóngyè Huáng

Observed names: H. -C. Huang, HUANG Hongye, Hongye HUANG, Hongye Huang, Huang, Hongye, Hòngyé Huáng
ORCID: 0000-0001-6071-2075
Observed ORCID: 0000-0001-6071-2075
OpenAlex ID: A5081527973
A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio
2019 · Jian Pang, Rui Wu, et al. · IEEE Journal of Solid-State Circuits · 233
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR
2020 · Jian Pang, Zheng Li, et al. · IEEE Journal of Solid-State Circuits · 203
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A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems
2021 · Jian Pang, Zheng Li, et al. · IEEE Journal of Solid-State Circuits · 105
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21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR
2019 · Jian Pang, Zheng Li, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 67
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS
2018 · Hanli Liu, Zheng Sun, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 65
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS
2018 · Hanli Liu, Zheng Sun, et al. · IEEE Journal of Solid-State Circuits · 54
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A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
2019 · Hanli Liu, Atsushi Shirane, et al. · IEEE Journal of Solid-State Circuits · 51
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter
2024 · Dingxin Xu, Zezheng Liu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 46
A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS
2020 · Bangan Liu, Yuncheng Zhang, et al. · IEEE Solid-State Circuits Letters · 36
A 28GHz CMOS Phased-Array Transceiver Featuring Gain Invariance Based on LO Phase Shifting Architecture with 0.1-Degree Beam-Steering Resolution for 5G New Radio
2018 · Jian Pang, Rui Wu, et al. · Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium · 36
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset
2024 · Chenxin Liu, Zheng Li, et al. · IEEE Journal of Solid-State Circuits · 31
A 32-kHz-Reference 2.4-GHz Fractional- N Oversampling PLL With 200-kHz Loop Bandwidth
2021 · Junjun Qiu, Zheng Sun, et al. · IEEE Journal of Solid-State Circuits · 31
A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation
2021 · Jian Pang, Zheng Li, et al. · Symposium on VLSI Circuits · 20
16.1 A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
2019 · Hanli Liu, Zheng Sun, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 18
A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch
2020 · Zheng Sun, Hanli Liu, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 16
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation
2020 · Jian Pang, Zheng Li, et al. · Symposium on VLSI Circuits · 16
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur
2024 · Dingxin Xu, Zezheng Liu, et al. · IEEE Journal of Solid-State Circuits · 13
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference
2023 · Dingxin Xu, Yuncheng Zhang, et al. · Custom Integrated Circuits Conference · 13
A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference
2024 · Dingxin Xu, Yuncheng Zhang, et al. · IEEE Journal of Solid-State Circuits · 12
A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver
2018 · Zheng Sun, Hanli Liu, et al. · European Solid-State Circuits Conference (ESSCIRC) · 12
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth
2021 · Junjun Qiu, Zheng Sun, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path
2023 · Waleed Madany, Yuncheng Zhang, et al. · European Solid-State Circuits Conference (ESSCIRC) · 10
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration
2023 · Junjun Qiu, Wenqian Wang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 10
A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR
2020 · Zheng Li, Jian Pang, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 10
A 150 GHz High-Power-Density Phased-Array Transceiver in 65nm CMOS for 6G UE Module
2025 · Yudai Yamazaki, Sunghwan Park, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 8
Works count: 57
Citation count: 1,176
H-index: 16
I10-index: 24
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