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Vasilii M. Khvatov

Observed names: V. M. Khvatov, V.M. Khvatov, Vasilii Mikhailovich Khvatov, Vasiliy Khvatov, Vasiliy M. Khvatov, В. М. Хватов, В.М. Хватов, Василий Михайлович Хватов
ORCID: 0000-0003-2285-4341
Observed ORCID: 0000-0003-2285-4341
OpenAlex ID: A5082049065
Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip
2019 · S. V. Gavrilov, D. A. Zheleznikov, et al. · Russian Microelectronics · 23
Clustering optimization based on simulated annealing algorithm for reconfigurable systems-on-chip
2018 · Sergey Gavrilov, Daniil Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 12
Solving the Problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip
2018 · S. V. Gavrilov, D. A. Zheleznikov, et al. · Russian Microelectronics · 7
Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip
2018 · IPPM RAS, S.V. Gavrilov, et al. · Problems of advanced micro- and nanoelectronic systems development · 7
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The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs
2018 · IPPM RAS, D.A. Zheleznikov, et al. · Problems of advanced micro- and nanoelectronic systems development · 7
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Solution of Interconnect Trace Tasks with Resynthesis for Reconfig-urable Systems-on-Chip
2017 · S.V. Gavrilov, D.A. Zheleznikov, et al. · Proceedings of Universities ELECTRONICS · 7
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Development of an IP-cores Libraries as Part of the Design Flow of Integrated Circuits on FPGA
2021 · Vasilii M. Khvatov, Daniil A. Zheleznikov · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 6
Маршрут топологического синтеза для реконфигурируемых систем на кристалле специального назначения
2019 · С. В. Гаврилов, Д. А. Железников, et al. · Микроэлектроника · 5
Development and Verification of Various Formats of Functional Blocks Libraries as a Part of the Design Flow for FPGAs
2019 · Tatiana V. Garbulina, Vasiliy M. Khvatov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 4
Development of the Trusted Tools for IC Design on Heterogeneous FPGAs
2023 · Sergey Vitalievich Gavrilov, Daniil Aleksandrovich Zheleznikov, et al. · Proceedings of the Institute for System Programming of RAS · 3
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Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs
2018 · IPPM RAS, V.M. Khvatov, et al. · Problems of advanced micro- and nanoelectronic systems development · 3
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Static Timing Analysis Method for Reconfigurable SoC with Various Types of Routing Resources
2023 · Vasilii M. Khvatov · Seminar on Electrical Engineering, Automation & Control Systems, Theory and Practical Applications (EEACS) · 2
Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs
2022 · V. M. Khvatov, S. V. Gavrilov · Russian Microelectronics · 2
Comparative Analysis of Clustering and Placement Methods for Reconfigurable System-on-Chips
2022 · IPPM RAS, P.I. Frolova, et al. · Problems of advanced micro- and nanoelectronic systems development · 2
Analysis of the Programmable Soft IP-cores Implementation for FPGAs
2021 · Vasilii M. Khvatov, Daniil A. Zheleznikov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 2
Complex Functional Block Libraries Formation in the Design Flow of User Circuits on FPGA and RSoC
2021 · V.M. Khvatov, S.V. Gavrilov · Proceedings of Universities ELECTRONICS · 2
Post-Route Performance Estimation Method for Reconfigurable Systems-on-a-Chip
2020 · Sergey V. Gavrilov, Vasilii M. Khvatov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 2
Development of a Method for Timing Analysis of Reconfigurable System-on-a-Chip Based on Models of Special Logic Elements
2020 · Dmitry V. Telpukhov, Roman A. Solovyev, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 2
Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip
2020 · IPPM RAS, S.V. Gavrilov, et al. · Problems of advanced micro- and nanoelectronic systems development · 2
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Development of a technique of fast timing analysis for the design of standard cells based on FinFET technology
2018 · Andrey Korshunov, Vasiliy Khvatov, et al. · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 2
A Set-Based Theoretical Model of IP-Cores for IC Design on Reconfigurable SoC
2024 · Sergey V. Gavrilov, Daniil A. Zheleznikov, et al. · IEEE International Conference on Problems of Informatics, Electronics and Radio Engineering (PIERE) · 1
The Method of Dynamic Characterization of Standard Cell Libraries for Field Programmable Gate Arrays
2023 · V. M. Khvatov, M. A. Zapletina · INFORMACIONNYE TEHNOLOGII · 1
Method for Determining the Optimal Composition of a Reduced Standard Cell Library for FPGA
2022 · Vasilii M. Khvatov, Daniil A. Zheleznikov · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · 1
Methods and algorithms of design on domestic FPGAs with given restrictions on routing resources
2018 · V. M. Khvatov, T V. Garbulina · Moscow Workshop on Electronic and Networking Technologies (MWENT) · 1
Method for Fast Evaluation of the Circuit Performance After Structural Resynthesis for RSoC
2022 · Vasilii M. Khvatov · Moscow Workshop on Electronic and Networking Technologies (MWENT)
Works count: 33
Citation count: 106
H-index: 6
I10-index: 2
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